AN 994: Drive-on-Chip Design Example for Intel Agilex® 7 Devices

ID 780361
Date 6/26/2023
Public
Document Table of Contents

5.2. Signal Scaling in the Software of the Drive-on-Chip Design Example

The software performs scaling to:
  • Normalize sigma-delta samples for use in the FOC algorithm
  • Apply zero offsets
  • Position feedback scaling

Figure 14. Signal Scaling ArchitectureThis figure shows a simplified block diagram of the scaling in the software application supporting the Tandem Motion-Power 48 V Board.

Scaling of Motor Phase Current Samples

The design treats motor phase current samples as dimensionless numbers in the FOC algorithm, rather than real current measurements.

To compensate for the differences in signal conditioning between the different ADCs, the design scales any other ADC samples as it reads them from the ADC to normalize them to represent the same physical quantity as the sigma-delta ADC samples.

Table 5.  Scaling of Intel Agilex® 7 Motor Phase Current Samples
Item Sigma-Delta
Motor Phase Currents 1024 counts/A
Scaling 1

Calculation of Zero Offsets

Offset errors arise in the ADC conversion process from a number of factors, including

  • Component tolerance in sense circuits
  • Offsets in sense amplifiers
  • Errors in Vdd supply to sense amplifiers and ADCs
  • Offsets in the ADC converters
Offsets are most noticeable when converting low level signals where they lead to a larger error in percentage terms. For the most crucial feedback, the design attempts to calculate and correct for the offsets.

Motor Phase Current Zero Offset

The design calculates the zero offset for the motor phase current during startup. the design samples several conversions while no motor current is flowing. The design averages the samples to calculate the offset. It applies them as a correction to the offset register in the sigma delta ADC module or stores them in the drive_params structure for use in software for other ADCs.