AN 994: Drive-on-Chip Design Example for Intel Agilex® 7 Devices

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ID 780361
Date 6/26/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the Drive-on-Chip Design Example for Intel Agilex® 7 Devices 2. Features of the Drive-on-Chip Design Example for Intel Agilex 7 Devices 3. Getting Started with the Drive-on-Chip Design Example for Intel Agilex 7 Devices 4. Rebuilding the Drive-on-Chip Design Example for Intel Agilex 7 Devices 5. About the Scaling of Feedback Signals 6. Motor Control Software 7. Functional Description of the Drive-on-Chip Design Example for Intel Agilex 7 Devices 8. Signals 9. Registers 10. Design Security Recommendations 11. Document Revision History for AN 994: Drive-on-Chip Design Example for Intel Agilex 7 Devices
3. Getting Started with the Drive-on-Chip Design Example for Intel Agilex 7 Devices x
3.1. Software Requirements for the Drive-on-Chip Design Example for Intel Agilex 7 Devices 3.2. Hardware Requirements for the Drive-on-Chip Design Example for Intel Agilex 7 Devices 3.3. Downloading and Installing the Design 3.4. Setting Up your Development Board for the Drive-on-Chip Design Example for Intel Agilex 7 Devices 3.5. Configuring the FPGA Hardware for the Drive-on-Chip Design Example for Intel Agilex 7 Devices 3.6. Programming the Nios V/g Software to the Device for the Drive-on-Chip Design Example for Intel Agilex 7 Devices 3.7. Debugging and Monitoring the Drive-on-Chip Design Example for Intel Agilex 7 Devices with Python GUI
3.7. Debugging and Monitoring the Drive-on-Chip Design Example for Intel Agilex 7 Devices with Python GUI x
3.7.1. GUI Control Parameters Pane for the Drive-on-Chip Design Example for Intel Agilex 7 Devices 3.7.2. GUI Main Panes for the Drive-on-Chip Design Example for Intel Agilex 7 Devices 3.7.3. Tuning the PI Controller Gains 3.7.4. Controlling the Speed and Position Demonstrations 3.7.5. Monitoring Performance
4. Rebuilding the Drive-on-Chip Design Example for Intel Agilex 7 Devices x
4.1. Generating the Platform Designer System 4.2. Compiling the Hardware in the Intel Quartus Prime Software 4.3. Generating and Building the Nios V/g BSP for the Drive-on-Chip Design Example 4.4. Software Application Configuration Files
4.4. Software Application Configuration Files x
4.4.1. Defining a New Motor or Encoder Type 4.4.2. Real Time Operating System Specific Configuration Files
5. About the Scaling of Feedback Signals x
5.1. Signal Sensing in Sigma-Delta 5.2. Signal Scaling in the Software of the Drive-on-Chip Design Example 5.3. Scale Factors for the Drive-on-Chip Design Example in the GUI
7. Functional Description of the Drive-on-Chip Design Example for Intel Agilex 7 Devices x
7.1. NiosV/g Processor Subsystem 7.2. Control Subsystem 7.3. Drive Subsystem 7.4. Motor and Power Board Model
7.3. Drive Subsystem x
7.3.1. Six-channel PWM Interface 7.3.2. Drive System Monitor 7.3.3. Quadrature Encoder Interface 7.3.4. Sigma-Delta ADC Interface for Drive Axes 7.3.5. Motor Control Modes 7.3.6. FOC Subsystem
7.3.2. Drive System Monitor x
7.3.2.1. Drive System Monitor States for the Drive-on-Chip Design Example
7.3.4. Sigma-Delta ADC Interface for Drive Axes x
7.3.4.1. Offset Adjustment for Sigma-Delta ADC Interface
7.3.6. FOC Subsystem x
7.3.6.1. DSP Builder for Intel FPGAs Model for the Drive-on-Chip Designs 7.3.6.2. Avalon Memory-Mapped Interface 7.3.6.3. About DSP Builder for Intel FPGAs 7.3.6.4. DSP Builder for Intel FPGAs Folding 7.3.6.5. DSP Builder for Intel FPGAs Design Guidelines 7.3.6.6. Generating VHDL for the DSP Builder Models for the Drive-on-Chip Designs
1. About the Drive-on-Chip Design Example for Intel Agilex® 7 Devices
2. Features of the Drive-on-Chip Design Example for Intel Agilex 7 Devices
3. Getting Started with the Drive-on-Chip Design Example for Intel Agilex 7 Devices
4. Rebuilding the Drive-on-Chip Design Example for Intel Agilex 7 Devices
5. About the Scaling of Feedback Signals
6. Motor Control Software
7. Functional Description of the Drive-on-Chip Design Example for Intel Agilex 7 Devices
8. Signals
9. Registers
10. Design Security Recommendations
11. Document Revision History for AN 994: Drive-on-Chip Design Example for Intel Agilex 7 Devices

3.6. Programming the Nios V/g Software to the Device for the Drive-on-Chip Design Example for Intel Agilex 7 Devices

  1. Program top.sof.
    The software is automatically copied to the CPU memories for running using .hex files located in <project>/software/dniosv_subsystem/build/bin/mem_init to initialize the memories in the system.
  2. Run the JTAG UART terminal to see the design software application output.
    Figure 5. Software application Output
  3. If you modify the software, program the Nios V soft processor using the command line:
    >>niosv-download <project>/software/dniosv_subsystem/build/bin/app.elf -g
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