AN 994: Drive-on-Chip Design Example for Intel Agilex® 7 Devices

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ID 780361
Date 6/26/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the Drive-on-Chip Design Example for Intel Agilex® 7 Devices 2. Features of the Drive-on-Chip Design Example for Intel Agilex 7 Devices 3. Getting Started with the Drive-on-Chip Design Example for Intel Agilex 7 Devices 4. Rebuilding the Drive-on-Chip Design Example for Intel Agilex 7 Devices 5. About the Scaling of Feedback Signals 6. Motor Control Software 7. Functional Description of the Drive-on-Chip Design Example for Intel Agilex 7 Devices 8. Signals 9. Registers 10. Design Security Recommendations 11. Document Revision History for AN 994: Drive-on-Chip Design Example for Intel Agilex 7 Devices
3. Getting Started with the Drive-on-Chip Design Example for Intel Agilex 7 Devices x
3.1. Software Requirements for the Drive-on-Chip Design Example for Intel Agilex 7 Devices 3.2. Hardware Requirements for the Drive-on-Chip Design Example for Intel Agilex 7 Devices 3.3. Downloading and Installing the Design 3.4. Setting Up your Development Board for the Drive-on-Chip Design Example for Intel Agilex 7 Devices 3.5. Configuring the FPGA Hardware for the Drive-on-Chip Design Example for Intel Agilex 7 Devices 3.6. Programming the Nios V/g Software to the Device for the Drive-on-Chip Design Example for Intel Agilex 7 Devices 3.7. Debugging and Monitoring the Drive-on-Chip Design Example for Intel Agilex 7 Devices with Python GUI
3.7. Debugging and Monitoring the Drive-on-Chip Design Example for Intel Agilex 7 Devices with Python GUI x
3.7.1. GUI Control Parameters Pane for the Drive-on-Chip Design Example for Intel Agilex 7 Devices 3.7.2. GUI Main Panes for the Drive-on-Chip Design Example for Intel Agilex 7 Devices 3.7.3. Tuning the PI Controller Gains 3.7.4. Controlling the Speed and Position Demonstrations 3.7.5. Monitoring Performance
4. Rebuilding the Drive-on-Chip Design Example for Intel Agilex 7 Devices x
4.1. Generating the Platform Designer System 4.2. Compiling the Hardware in the Intel Quartus Prime Software 4.3. Generating and Building the Nios V/g BSP for the Drive-on-Chip Design Example 4.4. Software Application Configuration Files
4.4. Software Application Configuration Files x
4.4.1. Defining a New Motor or Encoder Type 4.4.2. Real Time Operating System Specific Configuration Files
5. About the Scaling of Feedback Signals x
5.1. Signal Sensing in Sigma-Delta 5.2. Signal Scaling in the Software of the Drive-on-Chip Design Example 5.3. Scale Factors for the Drive-on-Chip Design Example in the GUI
7. Functional Description of the Drive-on-Chip Design Example for Intel Agilex 7 Devices x
7.1. NiosV/g Processor Subsystem 7.2. Control Subsystem 7.3. Drive Subsystem 7.4. Motor and Power Board Model
7.3. Drive Subsystem x
7.3.1. Six-channel PWM Interface 7.3.2. Drive System Monitor 7.3.3. Quadrature Encoder Interface 7.3.4. Sigma-Delta ADC Interface for Drive Axes 7.3.5. Motor Control Modes 7.3.6. FOC Subsystem
7.3.2. Drive System Monitor x
7.3.2.1. Drive System Monitor States for the Drive-on-Chip Design Example
7.3.4. Sigma-Delta ADC Interface for Drive Axes x
7.3.4.1. Offset Adjustment for Sigma-Delta ADC Interface
7.3.6. FOC Subsystem x
7.3.6.1. DSP Builder for Intel FPGAs Model for the Drive-on-Chip Designs 7.3.6.2. Avalon Memory-Mapped Interface 7.3.6.3. About DSP Builder for Intel FPGAs 7.3.6.4. DSP Builder for Intel FPGAs Folding 7.3.6.5. DSP Builder for Intel FPGAs Design Guidelines 7.3.6.6. Generating VHDL for the DSP Builder Models for the Drive-on-Chip Designs
1. About the Drive-on-Chip Design Example for Intel Agilex® 7 Devices
2. Features of the Drive-on-Chip Design Example for Intel Agilex 7 Devices
3. Getting Started with the Drive-on-Chip Design Example for Intel Agilex 7 Devices
4. Rebuilding the Drive-on-Chip Design Example for Intel Agilex 7 Devices
5. About the Scaling of Feedback Signals
6. Motor Control Software
7. Functional Description of the Drive-on-Chip Design Example for Intel Agilex 7 Devices
8. Signals
9. Registers
10. Design Security Recommendations
11. Document Revision History for AN 994: Drive-on-Chip Design Example for Intel Agilex 7 Devices

5.3. Scale Factors for the Drive-on-Chip Design Example in the GUI

The design applies scale factors to signals in the GUI for diagnostic display in human readable, physical units (e.g. volts, amps).
Table 6.  Scale Factors in the GUIThis table shows the scale factors that the GUI uses, based on the scaling of the motor phase currents as in Scaling of Motor Phase Current Samples.
Item Sigma Delta Scaling
Motor Phase Voltages 545 counts/A
DC Bus Voltage 545 counts/V
Input Voltage 895 counts/V
Input Current 252 counts/A
Inductor Current 717 counts/A
DC Bus Current 1638 counts/A
Motor Phase Currents 1.024 counts/mA
Table 7.  Scale Factors for Id and Iq in the GUIThe table shows that scaling of Id (requested and actual) and Iq (requested and actual) in the GUI is the same as the motor phase current scaling
Item Sigma Delta Scaling (counts/mA)
Id Direct Current 1.024
Iq Quadrature Current 1.024

SVM Voltage

The design calculates the maximum count of the PWM from the PWM frequency , and passes it to the software from the system.h header file generated with the Nios V/g BSP. The maximum count varies with the PWM clock frequency and sample rate and is (PWM frequency in Hz)/( (Sample rate) *1000). For example, with a PWM clock frequency of 300 MHz and a sample rate of 16 kHz the maximum count is 18,750.

Voltage demand signals for the PWM IP have a full-scale value equal to the maximum count, so setting the voltage demand to the maximum count value achieves 100% duty cycle and 100% of DC link voltage (in this board coming from the simulated power board). Setting the voltage demand to 0 achieves 0% duty cycle and 0% of the DC link voltage. By convention, voltages for display purposes are centred around 0. For example, if the DC link voltage is 48 V voltage demand signals between 0 and maximum count map to 0 to +48 V outputs, but these signals are offset and show in the GUI as -24 V to +24 V.

Using the above example of 300 MHz PWM and 16 kHz sample rate for the Tandem Motion-Power 48 V Board model, in the GUI:

Offset 18,750/2 = 9,375

Scaling 9,375/24 = 391

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