AN 994: Drive-on-Chip Design Example for Intel Agilex® 7 Devices

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ID 780361
Date 6/26/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the Drive-on-Chip Design Example for Intel Agilex® 7 Devices 2. Features of the Drive-on-Chip Design Example for Intel Agilex 7 Devices 3. Getting Started with the Drive-on-Chip Design Example for Intel Agilex 7 Devices 4. Rebuilding the Drive-on-Chip Design Example for Intel Agilex 7 Devices 5. About the Scaling of Feedback Signals 6. Motor Control Software 7. Functional Description of the Drive-on-Chip Design Example for Intel Agilex 7 Devices 8. Signals 9. Registers 10. Design Security Recommendations 11. Document Revision History for AN 994: Drive-on-Chip Design Example for Intel Agilex 7 Devices
3. Getting Started with the Drive-on-Chip Design Example for Intel Agilex 7 Devices x
3.1. Software Requirements for the Drive-on-Chip Design Example for Intel Agilex 7 Devices 3.2. Hardware Requirements for the Drive-on-Chip Design Example for Intel Agilex 7 Devices 3.3. Downloading and Installing the Design 3.4. Setting Up your Development Board for the Drive-on-Chip Design Example for Intel Agilex 7 Devices 3.5. Configuring the FPGA Hardware for the Drive-on-Chip Design Example for Intel Agilex 7 Devices 3.6. Programming the Nios V/g Software to the Device for the Drive-on-Chip Design Example for Intel Agilex 7 Devices 3.7. Debugging and Monitoring the Drive-on-Chip Design Example for Intel Agilex 7 Devices with Python GUI
3.7. Debugging and Monitoring the Drive-on-Chip Design Example for Intel Agilex 7 Devices with Python GUI x
3.7.1. GUI Control Parameters Pane for the Drive-on-Chip Design Example for Intel Agilex 7 Devices 3.7.2. GUI Main Panes for the Drive-on-Chip Design Example for Intel Agilex 7 Devices 3.7.3. Tuning the PI Controller Gains 3.7.4. Controlling the Speed and Position Demonstrations 3.7.5. Monitoring Performance
4. Rebuilding the Drive-on-Chip Design Example for Intel Agilex 7 Devices x
4.1. Generating the Platform Designer System 4.2. Compiling the Hardware in the Intel Quartus Prime Software 4.3. Generating and Building the Nios V/g BSP for the Drive-on-Chip Design Example 4.4. Software Application Configuration Files
4.4. Software Application Configuration Files x
4.4.1. Defining a New Motor or Encoder Type 4.4.2. Real Time Operating System Specific Configuration Files
5. About the Scaling of Feedback Signals x
5.1. Signal Sensing in Sigma-Delta 5.2. Signal Scaling in the Software of the Drive-on-Chip Design Example 5.3. Scale Factors for the Drive-on-Chip Design Example in the GUI
7. Functional Description of the Drive-on-Chip Design Example for Intel Agilex 7 Devices x
7.1. NiosV/g Processor Subsystem 7.2. Control Subsystem 7.3. Drive Subsystem 7.4. Motor and Power Board Model
7.3. Drive Subsystem x
7.3.1. Six-channel PWM Interface 7.3.2. Drive System Monitor 7.3.3. Quadrature Encoder Interface 7.3.4. Sigma-Delta ADC Interface for Drive Axes 7.3.5. Motor Control Modes Open Loop FOC with Position Sensor Feedback High-speed FOC with Position Sensor Feedback 7.3.6. FOC Subsystem
7.3.2. Drive System Monitor x
7.3.2.1. Drive System Monitor States for the Drive-on-Chip Design Example
7.3.4. Sigma-Delta ADC Interface for Drive Axes x
7.3.4.1. Offset Adjustment for Sigma-Delta ADC Interface
7.3.6. FOC Subsystem x
7.3.6.1. DSP Builder for Intel FPGAs Model for the Drive-on-Chip Designs 7.3.6.2. Avalon Memory-Mapped Interface 7.3.6.3. About DSP Builder for Intel FPGAs 7.3.6.4. DSP Builder for Intel FPGAs Folding 7.3.6.5. DSP Builder for Intel FPGAs Design Guidelines 7.3.6.6. Generating VHDL for the DSP Builder Models for the Drive-on-Chip Designs
1. About the Drive-on-Chip Design Example for Intel Agilex® 7 Devices
2. Features of the Drive-on-Chip Design Example for Intel Agilex 7 Devices
3. Getting Started with the Drive-on-Chip Design Example for Intel Agilex 7 Devices
4. Rebuilding the Drive-on-Chip Design Example for Intel Agilex 7 Devices
5. About the Scaling of Feedback Signals
6. Motor Control Software
7. Functional Description of the Drive-on-Chip Design Example for Intel Agilex 7 Devices
8. Signals
9. Registers
10. Design Security Recommendations
11. Document Revision History for AN 994: Drive-on-Chip Design Example for Intel Agilex 7 Devices

7.3.5. Motor Control Modes

The Drive-on-Chip Design Example supports various control algorithms and commutation modes.
The design supports:
  • Open-loop Volts/Hz speed control with sinusoidal commutation
  • Speed and position control with field-oriented current control (FOC), sinusoidal commutation with quadrature encoder or resolver feedback The design implements this mode in software or a combination of software and hardware using FOC IP.

Open Loop

The design supports open loop control using sinusoidal commutation and trapezoidal commutation. The design uses Volts per Hz control in which the voltage the design applies to the motor increases with increasing frequency (motor speed). After each interrupt the interrupt service routine (ISR) updates a ramp generator to represent the motor electrical angle based on the previous angle, desired speed, and sample rate. The ISR calculates the voltage to apply using a Volts per Hz control gain based on the frequency and motor parameters. In open loop sinusoidal commutation, the ISR applies the inverse Park Transform and SVM function from FOC to generate sinusoidal commutation.
Figure 27. Open Loop Sinusoidal Commutation

FOC with Position Sensor Feedback

The design supports FOC sensor control where the motor position feeds back to form a closed loop with position and speed PI control. The design senses the motor position by incremental (quadrature) encoders.

The design samples and uses the motor phase currents as feedback to the FOC algorithm.
Figure 28. FOC with Position Sensor Feedback

High-speed FOC with Position Sensor Feedback

The high-speed FOC sensor mode closely resembles the standard FOC with position sensor feedback mode, but operates at 64 kHz instead of 16 or 32 kHz. In this mode, the design performs the FOC calculation only with the FOC DSP Builder IP. Phase currents U and W are directly connected to the sigma-delta ADC interface. The output space vector modulation PWM values are directly connected to the six-channel PWM interface.

The ADC interface operates at 64 kHz and is synchronized with the PWM to eliminate FET switching noise from the power board. The software can run at 96 kHz, but the Tandem board limits the frequency to 64 kHz. The high-speed mode only supports the DSP Builder fixed-point design. It does not support floating point or software fixed point.

Figure 29. Block diagram for high-speed FOC connection

The figure shows the high-speed FOC connection. In the diagram, bold lines represent the Avalon interface, single lines indicate the direct interface, and blue lines indicate one item triggers the next. ISR uses interface IP and algorithm acceleration IPs for control and diagnostics. The ISR calls Avalon memory-mapped interfaces

Figure 30. Timing diagram for high-speed FOC The figure shows the timing diagram for the high-speed FOC. Although the software operates at 32 kHz, the FOC DSP IP receives input and output updates at a frequency of 64 kHz.

PWM counter values reaching PWM_TRIGGER_UP and PWM_TRIGGER_DOWN initiate ADC conversion for feedback-current readings. When the ADC reading stabilizes, the latch_en signal is set to high. The avs_irq signal activates each ISR service routine, determined by the irq_counter and latch_en. The irq_counter value ensures sufficient time for each ISR service routine and is automatically calculated in the software based on the FOC running speed.

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