AN 967: Multiple Device Synchronization in Digital Phased Array System

Download PDF
ID 734485
Date 12/15/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Digital Phased Array Synchronization 3. Multiple Device Synchronization in DPA System 4. Test Result 5. Conclusion 6. Document Revision History for AN 967: Multiple Device Synchronization in Digital Phased Array System A. Appendix
3. Multiple Device Synchronization in DPA System x
3.1. JESD204(A/B/C) Interface 3.2. Clock/SYSREF Scheme 3.3. FPGA Design Synchronization 3.4. Data Exchange between FPGA Devices 3.5. Event Trigger Synchronization
3.2. Clock/SYSREF Scheme x
3.2.1. clk_ref 3.2.2. clk_dev and SYSREF 3.2.3. SYSREF Capture
3.3. FPGA Design Synchronization x
3.3.1. Data and SYSREF Clock Domain Crossing 3.3.2. Data Transformation when Clock Domain Crossing
3.5. Event Trigger Synchronization x
3.5.1. SYSREF Distribution
A. Appendix x
A.1. FPGA I/O Timing Constraints for SYSREF
A.1. FPGA I/O Timing Constraints for SYSREF x
A.1.1. Source-Synchronous Interface Timing Constraints A.1.2. SYSREF I/O Timing Closure
A.1.2. SYSREF I/O Timing Closure x
A.1.2.1. Adjust Input Delay Chain Value A.1.2.2. Using PLL to Adjust clk_dev Phase A.1.2.3. Place First SYSREF Capture Register in IOE
1. Introduction
2. Digital Phased Array Synchronization
3. Multiple Device Synchronization in DPA System
4. Test Result
5. Conclusion
6. Document Revision History for AN 967: Multiple Device Synchronization in Digital Phased Array System
A. Appendix

A.1.2.2. Using PLL to Adjust clk_dev Phase

If the timing is still not met after adjusting the delay of the programmable input delay chain, you can use a PLL to shift the clk_dev phase and use the PLL output clock to capture the SYSREF as shown in the following figure.
Figure 20. PLL Provides Clock Shift

If PLL is used to provide the phase shift for clk_dev, you do not need to adjust the delay of the programmable input delay chain. Instead, set the input delay chain value to 0. Additionally, place the first SYSREF capture register in the IOE to reduce the trace delay from I/O pin to the register input. All these operations aim at reducing the delta part of the delay in different PVT, making it easier to meet timing in all the timing models, across different voltage, and temperature variations.

Level Two Title