AN 967: Multiple Device Synchronization in Digital Phased Array System

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ID 734485
Date 12/15/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Digital Phased Array Synchronization 3. Multiple Device Synchronization in DPA System 4. Test Result 5. Conclusion 6. Document Revision History for AN 967: Multiple Device Synchronization in Digital Phased Array System A. Appendix
3. Multiple Device Synchronization in DPA System x
3.1. JESD204(A/B/C) Interface 3.2. Clock/SYSREF Scheme 3.3. FPGA Design Synchronization 3.4. Data Exchange between FPGA Devices 3.5. Event Trigger Synchronization
3.2. Clock/SYSREF Scheme x
3.2.1. clk_ref 3.2.2. clk_dev and SYSREF 3.2.3. SYSREF Capture
3.3. FPGA Design Synchronization x
3.3.1. Data and SYSREF Clock Domain Crossing 3.3.2. Data Transformation when Clock Domain Crossing
3.5. Event Trigger Synchronization x
3.5.1. SYSREF Distribution
A. Appendix x
A.1. FPGA I/O Timing Constraints for SYSREF
A.1. FPGA I/O Timing Constraints for SYSREF x
A.1.1. Source-Synchronous Interface Timing Constraints A.1.2. SYSREF I/O Timing Closure
A.1.2. SYSREF I/O Timing Closure x
A.1.2.1. Adjust Input Delay Chain Value A.1.2.2. Using PLL to Adjust clk_dev Phase A.1.2.3. Place First SYSREF Capture Register in IOE
1. Introduction
2. Digital Phased Array Synchronization
3. Multiple Device Synchronization in DPA System
4. Test Result
5. Conclusion
6. Document Revision History for AN 967: Multiple Device Synchronization in Digital Phased Array System
A. Appendix

A.1.2.1. Adjust Input Delay Chain Value

There is a programmable delay chain in the IOE. You can set the delay value in Quartus -> Assignment Editor, as shown in the following figure. The sysref_in is the SYSREF pin name in FPGA project.
Figure 19. Input Delay Chain Setting

The value 0 means minimum delay. Increasing the delay value increases the physical delay of the delay chain.

After changing the programmable input delay chain value, you must re-compile the FPGA project and check the I/O timing again. It needs several iterations to find the suitable delay value.

Intel recommends that you set the delay value as small as possible. A smaller delay has a smaller delta part in different PVT, making it easier to meet timing in different timing models.

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