AN 967: Multiple Device Synchronization in Digital Phased Array System

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ID 734485
Date 12/15/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Digital Phased Array Synchronization 3. Multiple Device Synchronization in DPA System 4. Test Result 5. Conclusion 6. Document Revision History for AN 967: Multiple Device Synchronization in Digital Phased Array System A. Appendix
3. Multiple Device Synchronization in DPA System x
3.1. JESD204(A/B/C) Interface 3.2. Clock/SYSREF Scheme 3.3. FPGA Design Synchronization 3.4. Data Exchange between FPGA Devices 3.5. Event Trigger Synchronization
3.2. Clock/SYSREF Scheme x
3.2.1. clk_ref 3.2.2. clk_dev and SYSREF 3.2.3. SYSREF Capture
3.3. FPGA Design Synchronization x
3.3.1. Data and SYSREF Clock Domain Crossing 3.3.2. Data Transformation when Clock Domain Crossing
3.5. Event Trigger Synchronization x
3.5.1. SYSREF Distribution
A. Appendix x
A.1. FPGA I/O Timing Constraints for SYSREF
A.1. FPGA I/O Timing Constraints for SYSREF x
A.1.1. Source-Synchronous Interface Timing Constraints A.1.2. SYSREF I/O Timing Closure
A.1.2. SYSREF I/O Timing Closure x
A.1.2.1. Adjust Input Delay Chain Value A.1.2.2. Using PLL to Adjust clk_dev Phase A.1.2.3. Place First SYSREF Capture Register in IOE
1. Introduction
2. Digital Phased Array Synchronization
3. Multiple Device Synchronization in DPA System
4. Test Result
5. Conclusion
6. Document Revision History for AN 967: Multiple Device Synchronization in Digital Phased Array System
A. Appendix

3.4. Data Exchange between FPGA Devices

In the figure Clocks and JESD204B/C Interface in DPA System Synchronization in Clock/SYSREF Scheme the beamformer output of FPGA B is sent to FPGA A, combined with the beamformer output of FPGA A, and finally summed to get the beamforming result of all 8 DPA elements. It requires the FPGA A beamformer output and FPGA B beamformer output to be synchronized when combined in FPGA A.

The JESD204B/C transfers data from FPGA B to FPGA A. Deterministic latency feature guarantees a fixed latency from FPGA B to FPGA A across different power cycles and PVT variations. If using other interconnect protocols, for example, Ethernet or Serial Lite, you must design an extra logic to synchronize two FPGA devices’ data exchange. It makes the system development more complex.

In the following figure, the shift-registers in FPGA A compensate the latency because the JESD204B/C latency is deterministic.

Figure 14. Data Exchange between FPGA Devices
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