AN 967: Multiple Device Synchronization in Digital Phased Array System

Download PDF
ID 734485
Date 12/15/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Digital Phased Array Synchronization 3. Multiple Device Synchronization in DPA System 4. Test Result 5. Conclusion 6. Document Revision History for AN 967: Multiple Device Synchronization in Digital Phased Array System A. Appendix
3. Multiple Device Synchronization in DPA System x
3.1. JESD204(A/B/C) Interface 3.2. Clock/SYSREF Scheme 3.3. FPGA Design Synchronization 3.4. Data Exchange between FPGA Devices 3.5. Event Trigger Synchronization
3.2. Clock/SYSREF Scheme x
3.2.1. clk_ref 3.2.2. clk_dev and SYSREF 3.2.3. SYSREF Capture
3.3. FPGA Design Synchronization x
3.3.1. Data and SYSREF Clock Domain Crossing 3.3.2. Data Transformation when Clock Domain Crossing
3.5. Event Trigger Synchronization x
3.5.1. SYSREF Distribution
A. Appendix x
A.1. FPGA I/O Timing Constraints for SYSREF
A.1. FPGA I/O Timing Constraints for SYSREF x
A.1.1. Source-Synchronous Interface Timing Constraints A.1.2. SYSREF I/O Timing Closure
A.1.2. SYSREF I/O Timing Closure x
A.1.2.1. Adjust Input Delay Chain Value A.1.2.2. Using PLL to Adjust clk_dev Phase A.1.2.3. Place First SYSREF Capture Register in IOE
1. Introduction
2. Digital Phased Array Synchronization
3. Multiple Device Synchronization in DPA System
4. Test Result
5. Conclusion
6. Document Revision History for AN 967: Multiple Device Synchronization in Digital Phased Array System
A. Appendix

3.5.1. SYSREF Distribution

Many different system events are triggered by SYSREF. However, there is only one SYSREF signal connected to FPGA in most cases. Consequently, you need to distribute SYSREF internally inside FPGA.

The following figure shows the SYSREF capture and distribution logic.

Figure 15. SYSREF Capture and Distribution

The SYSREF distributor copies the recovered sysref_rcvd to its outputs based on the SYSREF_mask signal. The SYSREF_mask signal width equals to the number of the output ports. Each bit controls whether to copy SYSREF to the corresponding output port. Multiple bits of the SYSREF_mask signal can be set to copy SYSREF to multiple output ports. However, in most cases, SYSREF_mask is a one-hot signal and only one output port can receive SYSREF.

Level Two Title