AN 967: Multiple Device Synchronization in Digital Phased Array System

Download PDF
ID 734485
Date 12/15/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Digital Phased Array Synchronization 3. Multiple Device Synchronization in DPA System 4. Test Result 5. Conclusion 6. Document Revision History for AN 967: Multiple Device Synchronization in Digital Phased Array System A. Appendix
3. Multiple Device Synchronization in DPA System x
3.1. JESD204(A/B/C) Interface 3.2. Clock/SYSREF Scheme 3.3. FPGA Design Synchronization 3.4. Data Exchange between FPGA Devices 3.5. Event Trigger Synchronization
3.2. Clock/SYSREF Scheme x
3.2.1. clk_ref 3.2.2. clk_dev and SYSREF 3.2.3. SYSREF Capture
3.3. FPGA Design Synchronization x
3.3.1. Data and SYSREF Clock Domain Crossing 3.3.2. Data Transformation when Clock Domain Crossing
3.5. Event Trigger Synchronization x
3.5.1. SYSREF Distribution
A. Appendix x
A.1. FPGA I/O Timing Constraints for SYSREF
A.1. FPGA I/O Timing Constraints for SYSREF x
A.1.1. Source-Synchronous Interface Timing Constraints A.1.2. SYSREF I/O Timing Closure
A.1.2. SYSREF I/O Timing Closure x
A.1.2.1. Adjust Input Delay Chain Value A.1.2.2. Using PLL to Adjust clk_dev Phase A.1.2.3. Place First SYSREF Capture Register in IOE
1. Introduction
2. Digital Phased Array Synchronization
3. Multiple Device Synchronization in DPA System
4. Test Result
5. Conclusion
6. Document Revision History for AN 967: Multiple Device Synchronization in Digital Phased Array System
A. Appendix

3.1. JESD204(A/B/C) Interface

The JEDEC committee created the JESD204 data converter serial interface standard to standardize and reduce the number of data inputs/outputs between high-speed data converters and other devices, such as FPGAs.

JESD204 Serial Interface has several versions:

  • JESD204
  • JESD204A
  • JESD204B
  • JESD204C

JESD204B and JESD204C subclass 1 mode provides the deterministic latency feature based on the sideband SYSREF signal, and makes the multi-channel or device synchronization easy to implement.

Table 3.  Brief Information About JESD204B Intel FPGA IP CoreThe following table gives information about JESD204B Intel FPGA IP core.
Features Description
Protocol Features
  • Joint Electron Device Engineering Council (JEDEC) JESD204B.01, 2012 standard release specification
  • Device subclass:
    • Subclass 0—Backwards compatible to JESD204A.
    • Subclass 1—Uses SYSREF signal to support deterministic latency.
    • Subclass 2—Uses SYNC_N detection to support deterministic latency.
Core Features
  • Run-time configuration of parameters L, M, and F
  • Data rate of up to 12.5 gigabits per second (Gbps)—per JESD204B specification
  • Single or multiple lanes (up to 8 lanes per link)
  • Serial lane alignment and monitoring
  • Lane synchronization
  • Modular design that supports multidevice synchronization
  • Deterministic latency support
  • 8B/10B encoding
  • Scrambling/Descrambling
Device Family Support
  • Intel Agilex® 7 devices (E-Tile/F-Tile)
  • Intel® Stratix® 10 FPGA devices (L-Tile/H-Tile/E-Tile)
  • Intel® Arria® 10 FPGA devices
  • Intel® Cyclone® 10 GX FPGA devices
  • Stratix® V FPGA devices
Table 4.  Brief Information about JESD204C Intel FPGA IP CoreThe following table gives information about JESD204C Intel FPGA IP core.
Features Description
Protocol Features
  • Joint Electron Device Engineering Council (JEDEC) JESD204C standard 2017
  • Device subclass:
    • Subclass 0—No deterministic latency.
    • Subclass 1—Uses SYSREF signal to support deterministic latency
Core Features
  • Data rate of up to 28.9 Gbps for Intel Agilex® 7 and Intel® Stratix® 10 (E-Tile) devices, 32.44032 Gbps for Intel Agilex® 7 (F-Tile) devices
  • Single or multiple lanes (up to 16 lanes per link)
  • Local extended multiblock clock (LEMC) counter based on E=1 to 256 for Intel Agilex® 7 and Intel® Stratix® 10 (E-Tile) devices, E=1 to 32 for Intel Agilex® 7 (F-Tile) devices
  • Serial lane alignment and monitoring
  • Lane synchronization
  • Modular design that supports multidevice synchronization
  • MAC and PHY partitioning
  • Deterministic latency support
  • 64B/66B encoding
  • Scrambling/Descrambling
  • Bonded and non-bonded TX PMA mode
  • Optional support for ECC M20K DCFIFO
  • Options for sync header configurations
    • CRC-12
    • Standalone command channels
Device Family Support
  • Intel Agilex® 7 and Intel® Stratix® 10 (E-Tile) FPGA devices
  • Intel Agilex® 7 (F-Tile) FPGA devices
Level Two Title