AN 967: Multiple Device Synchronization in Digital Phased Array System

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ID 734485
Date 12/15/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Digital Phased Array Synchronization 3. Multiple Device Synchronization in DPA System 4. Test Result 5. Conclusion 6. Document Revision History for AN 967: Multiple Device Synchronization in Digital Phased Array System A. Appendix
3. Multiple Device Synchronization in DPA System x
3.1. JESD204(A/B/C) Interface 3.2. Clock/SYSREF Scheme 3.3. FPGA Design Synchronization 3.4. Data Exchange between FPGA Devices 3.5. Event Trigger Synchronization
3.2. Clock/SYSREF Scheme x
3.2.1. clk_ref 3.2.2. clk_dev and SYSREF 3.2.3. SYSREF Capture
3.3. FPGA Design Synchronization x
3.3.1. Data and SYSREF Clock Domain Crossing 3.3.2. Data Transformation when Clock Domain Crossing
3.5. Event Trigger Synchronization x
3.5.1. SYSREF Distribution
A. Appendix x
A.1. FPGA I/O Timing Constraints for SYSREF
A.1. FPGA I/O Timing Constraints for SYSREF x
A.1.1. Source-Synchronous Interface Timing Constraints A.1.2. SYSREF I/O Timing Closure
A.1.2. SYSREF I/O Timing Closure x
A.1.2.1. Adjust Input Delay Chain Value A.1.2.2. Using PLL to Adjust clk_dev Phase A.1.2.3. Place First SYSREF Capture Register in IOE
1. Introduction
2. Digital Phased Array Synchronization
3. Multiple Device Synchronization in DPA System
4. Test Result
5. Conclusion
6. Document Revision History for AN 967: Multiple Device Synchronization in Digital Phased Array System
A. Appendix

6. Document Revision History for AN 967: Multiple Device Synchronization in Digital Phased Array System

Document Version Changes
2023.12.15
  • Updated description for Core Features from 32 Gbps to 32.44032 Gbps in Brief Information about JESD204C Intel® FPGA IP Core table in JESD204(A/B/C) Interface section.
  • Updated clk_dev and SYSREF section with additional definition for clk_dev.
  • Updated all instances of data_clock to frame_clock in Data and SYSREF Clock Domain Crossing and Data Transformation when Clock Domain Crossing sections.
2023.03.27 Updated product family name to "Intel Agilex® 7".
2022.08.12 Initial release.
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