AN 967: Multiple Device Synchronization in Digital Phased Array System

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ID 734485
Date 12/15/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Digital Phased Array Synchronization 3. Multiple Device Synchronization in DPA System 4. Test Result 5. Conclusion 6. Document Revision History for AN 967: Multiple Device Synchronization in Digital Phased Array System A. Appendix
3. Multiple Device Synchronization in DPA System x
3.1. JESD204(A/B/C) Interface 3.2. Clock/SYSREF Scheme 3.3. FPGA Design Synchronization 3.4. Data Exchange between FPGA Devices 3.5. Event Trigger Synchronization
3.2. Clock/SYSREF Scheme x
3.2.1. clk_ref 3.2.2. clk_dev and SYSREF 3.2.3. SYSREF Capture
3.3. FPGA Design Synchronization x
3.3.1. Data and SYSREF Clock Domain Crossing 3.3.2. Data Transformation when Clock Domain Crossing
3.5. Event Trigger Synchronization x
3.5.1. SYSREF Distribution
A. Appendix x
A.1. FPGA I/O Timing Constraints for SYSREF
A.1. FPGA I/O Timing Constraints for SYSREF x
A.1.1. Source-Synchronous Interface Timing Constraints A.1.2. SYSREF I/O Timing Closure
A.1.2. SYSREF I/O Timing Closure x
A.1.2.1. Adjust Input Delay Chain Value A.1.2.2. Using PLL to Adjust clk_dev Phase A.1.2.3. Place First SYSREF Capture Register in IOE
1. Introduction
2. Digital Phased Array Synchronization
3. Multiple Device Synchronization in DPA System
4. Test Result
5. Conclusion
6. Document Revision History for AN 967: Multiple Device Synchronization in Digital Phased Array System
A. Appendix

4. Test Result

The test result is based on Intel® Stratix® 10 FPGA.

The following figure shows the test system infrastructure. The clock/SYSREF scheme is the same as that shown in Clocks and JESD204B/C Interface in DPA System Synchronization in Clock/SYSREF Scheme.

The differences between the test system and the example in Multiple Device Synchronization in DPA System in Digital Phased Array Synchronization are listed below:

  • All ADCs are driven by a common signal generator. The misalignment in the analog path (part I in the diagram) is already compensated by the ADC device calibration and cable or trace delay compensation.
  • There are 8 ADC channels for each FPGA device, we can test 16 ADC channels synchronization.
  • All the digital delay modules in FPGA are set to 0, so all ADC channels’ waveforms should overlap when the system is synchronized.
  • Remove the combiners. Instead, transfer all 8 channels’ waveforms from FPGA B to FPGA A by JESD204C. In FPGA A, hardware capture module captures 16 channels’ waveforms and transfer to the host. If the system is synchronized, all 16 channels’ waveforms should overlap.
Figure 16. Test System

The following figure shows the waveforms captured by the hardware capture module in FPGA A. All 16 channels’ waveforms (8 local channels and 8 remote channels) overlap. It illustrates that all local and remote channels are synchronized.

Figure 17. On-Board Test Result of Multiple Device Synchronization
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