AN 967: Multiple Device Synchronization in Digital Phased Array System

Download PDF
ID 734485
Date 12/15/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Digital Phased Array Synchronization 3. Multiple Device Synchronization in DPA System 4. Test Result 5. Conclusion 6. Document Revision History for AN 967: Multiple Device Synchronization in Digital Phased Array System A. Appendix
3. Multiple Device Synchronization in DPA System x
3.1. JESD204(A/B/C) Interface 3.2. Clock/SYSREF Scheme 3.3. FPGA Design Synchronization 3.4. Data Exchange between FPGA Devices 3.5. Event Trigger Synchronization
3.2. Clock/SYSREF Scheme x
3.2.1. clk_ref 3.2.2. clk_dev and SYSREF 3.2.3. SYSREF Capture
3.3. FPGA Design Synchronization x
3.3.1. Data and SYSREF Clock Domain Crossing 3.3.2. Data Transformation when Clock Domain Crossing
3.5. Event Trigger Synchronization x
3.5.1. SYSREF Distribution
A. Appendix x
A.1. FPGA I/O Timing Constraints for SYSREF
A.1. FPGA I/O Timing Constraints for SYSREF x
A.1.1. Source-Synchronous Interface Timing Constraints A.1.2. SYSREF I/O Timing Closure
A.1.2. SYSREF I/O Timing Closure x
A.1.2.1. Adjust Input Delay Chain Value A.1.2.2. Using PLL to Adjust clk_dev Phase A.1.2.3. Place First SYSREF Capture Register in IOE
1. Introduction
2. Digital Phased Array Synchronization
3. Multiple Device Synchronization in DPA System
4. Test Result
5. Conclusion
6. Document Revision History for AN 967: Multiple Device Synchronization in Digital Phased Array System
A. Appendix

3.2.1. clk_ref

The clk_ref must be a low jitter signal and all clk_ref clocks must be derived from the same source. This source must be split and distributed to all ADCs with the same delay.

The following figure shows four ADC waveforms are synchronized when the clk_ref signals of all the ADCs are from the same source. The delays of all clk_ref signals are matched exactly. When the waveforms are synchronized, all channels’ waveforms overlap.

Figure 5. ADC Waveforms when clk_ref is from the Same Source

The following figure demonstrates the importance of having all clk_ref derived from the same root clock. The figure shows four ADC waveforms when the clk_ref signals of all the ADCs are from the different sources. Differential phase offset wander causes time dependent misalignment between different ADCs. This must be avoided in the clock scheme.

Figure 6. ADC Waveforms when clk_ref is from the Different Sources
Level Two Title