AN 967: Multiple Device Synchronization in Digital Phased Array System

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ID 734485
Date 12/15/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Digital Phased Array Synchronization 3. Multiple Device Synchronization in DPA System 4. Test Result 5. Conclusion 6. Document Revision History for AN 967: Multiple Device Synchronization in Digital Phased Array System A. Appendix
3. Multiple Device Synchronization in DPA System x
3.1. JESD204(A/B/C) Interface 3.2. Clock/SYSREF Scheme 3.3. FPGA Design Synchronization 3.4. Data Exchange between FPGA Devices 3.5. Event Trigger Synchronization
3.2. Clock/SYSREF Scheme x
3.2.1. clk_ref 3.2.2. clk_dev and SYSREF 3.2.3. SYSREF Capture
3.3. FPGA Design Synchronization x
3.3.1. Data and SYSREF Clock Domain Crossing 3.3.2. Data Transformation when Clock Domain Crossing
3.5. Event Trigger Synchronization x
3.5.1. SYSREF Distribution
A. Appendix x
A.1. FPGA I/O Timing Constraints for SYSREF
A.1. FPGA I/O Timing Constraints for SYSREF x
A.1.1. Source-Synchronous Interface Timing Constraints A.1.2. SYSREF I/O Timing Closure
A.1.2. SYSREF I/O Timing Closure x
A.1.2.1. Adjust Input Delay Chain Value A.1.2.2. Using PLL to Adjust clk_dev Phase A.1.2.3. Place First SYSREF Capture Register in IOE
1. Introduction
2. Digital Phased Array Synchronization
3. Multiple Device Synchronization in DPA System
4. Test Result
5. Conclusion
6. Document Revision History for AN 967: Multiple Device Synchronization in Digital Phased Array System
A. Appendix

3.3.2. Data Transformation when Clock Domain Crossing

clk_dev is the device clock generated by the clock device. It is the clock source of the FPGA device and drives the digital circuit and I/O of the data converter. clk_dev is used to capture the SYSREF signal at the destination device.

link_clock is the timing reference for the JESD204B/C Intel® FPGA IP core. For the JESD204B Intel® FPGA IP core, the link_clock runs at data rate/40 because the IP core operates in a 32-bit data bus architecture after 8B/10B encoding. For the JESD204C Intel® FPGA IP core, the link_clock is line rate divided by 132 because the link_clock operates in a 132-bit data bus domain architecture after 64B/66B encoding. For the JESD204B/C subclass 1, to avoid half link clock latency variation, you must supply the clk_dev at the same frequency as the link_clock.

frame_clock is the clock of the user logic in FPGA.

In Data and SYSREF Clock Domain Crossing, it states that frame_clock frequency is a multiple of the link_clock frequency. When data is transferred from the frame_clock domain to the link_clock domain, multiple clock cycles’ data are merged into a single beat wider data in the link_clock domain. Conversely, when data is transferred from the link_clock domain to the frame_clock domain, wider data is split into narrower data and assigned to different frame_clock cycles.

The following figure shows an example of data transformation from the link_clock domain to the frame_clock domain. The frame_clock to link_clock frequency ratio is 2:1. The phase_clock is generated by the same PLL as link_clock but with a 90 degree phase shift. It is used to locate the boundary of the link_clock data.

Figure 11. Data from link_clock Domain to frame_clock Domain

The following figure shows an example of data transformation from the frame_clock domain to the link_clock domain. The link_clock to frame_clock frequency ratio is 1:2.

Figure 12. Data from frame_clock Domain to link_clock Domain

The following figure shows the link_clock, frame_clock, and phase_clock that need to be generated by the same PLL, based on clk_dev.

Figure 13. Clocks Relationship
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