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1. About the RiscFree* IDE
2. Getting Started with the Ashling* RiscFree* IDE for Intel® FPGAs
3. Using Ashling* RiscFree* IDE for Intel® FPGAs with Nios® V Processor System
4. Using Ashling* RiscFree* IDE for Intel® FPGAs with Arm* Hard Processor System
5. Debugging Features with RiscFree* IDE for Intel® FPGAs
6. Debugging with Command-Line Interface
7. Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide Archives
8. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide
A. Appendix
3.1. Importing Nios® V Processor Project
3.2. Building Nios® V Processor Project
3.3. Setting Run Configuration to Download Nios® V Processor Project
3.4. Setting Debug Configuration to Debug Nios® V Processor Project
3.5. Setting Debug Configuration to Debug a Booting Nios® V Processor Project
3.6. Debugging Tools
5.1. Debug Features in RiscFree* IDE
5.2. Processor System Debug
5.3. Heterogeneous Multicore Debug
5.4. Debugging µC/OS-II Application
5.5. Debugging FreeRTOS Application
5.6. Debugging Zephyr Application
5.7. Arm* HPS On-Chip Trace
5.8. Debugging the Arm* Linux Kernel
5.9. Debugging Target Software in an Intel® Simics Simulator Session
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6.1. Running Ashling* GBD Server
The Ashling* GDBServer connects to the processor core with a remote GDB, which allows you to debug the software applications remotely. The Ashling* GDBServer must be ready before running the GDB.
Processor Core | Executables File |
---|---|
Nios® V Processor | <Intel Quartus Prime installation directory>/riscfree/debugger/gdbserver-riscv/ash-riscv-gdb-server.exe |
Arm* HPS core | <Intel Quartus Prime installation directory>/riscfree/debugger/gdbserver-arm/ash-arm-gdb-server.exe |
By invoking the Ashling* GDBServer with --help, you can get more information from the executables’ internal documentation about the supported GDB MONITOR commands. The table below lists the common options for starting the Ashling* GDBServer.
Options | Mandatory | Description |
---|---|---|
--device <IDCODE> | Yes | Specifies the IDCODE of the target device. Use jtagconfig to display the device IDCODE. |
--autodetect true | Yes | Enable JTAG scan chain auto-detection on the specified IDCODE. |
--probe-type usb-blaster-2 | Yes | Select Intel® FPGA Download Cable II (USB-Blaster 2) as the debug probe. |
--tap-number <number> | No | Select the TAP (test access port) with the specified IDCODE (when there is more than one TAP with the same IDCODE). |
--core-number <number> | No | Select the processor core within the same device.
|
--jtag-frequency <frequency> | No |
Specifies the JTAG frequency. The following are the valid inputs:
|
--list-probes | No | List out all the serial number for the connected debug probes. |
--instance <number> | No | Select the probe based on the serial number (persistent ID). Apply Ashling GDBServer with --list-probes to determine the serial number. |
--gdb-port <port> | No | Specifies the TCP port to connect to GDB. Default TCP at 2331. |