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1. About the RiscFree* IDE
2. Getting Started with the Ashling* RiscFree* IDE for Intel® FPGAs
3. Using Ashling* RiscFree* IDE for Intel® FPGAs with Nios® V Processor System
4. Using Ashling* RiscFree* IDE for Intel® FPGAs with Arm* Hard Processor System
5. Debugging Features with RiscFree* IDE for Intel® FPGAs
6. Debugging with Command-Line Interface
7. Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide Archives
8. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide
A. Appendix
3.1. Importing Nios® V Processor Project
3.2. Building Nios® V Processor Project
3.3. Setting Run Configuration to Download Nios® V Processor Project
3.4. Setting Debug Configuration to Debug Nios® V Processor Project
3.5. Setting Debug Configuration to Debug a Booting Nios® V Processor Project
3.6. Debugging Tools
5.1. Debug Features in RiscFree* IDE
5.2. Processor System Debug
5.3. Heterogeneous Multicore Debug
5.4. Debugging µC/OS-II Application
5.5. Debugging FreeRTOS Application
5.6. Debugging Zephyr Application
5.7. Arm* HPS On-Chip Trace
5.8. Debugging the Arm* Linux Kernel
5.9. Debugging Target Software in an Intel® Simics Simulator Session
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3.4. Setting Debug Configuration to Debug Nios® V Processor Project
Debug Configuration reuses the setting made in Run Configuration. If you have completed the setting, you can skip this subchapter.
You can download and debug the Nios® V processor software project on the targeted Intel FPGA using the RiscFree* IDE for Intel® FPGAs. To debug the project, follow these steps:
- Right-click the project folder (application or BSP) in the project explorer and select Debug As > Debug configurations.
- Select Ashling RISC-V Hardware Debugging > <Project Name>. Ensure the Project and C/C++ Application match your project name and project .elf file, respectively.
- Under the Main tab, for C/C++ Application, browse to select the application build .elf file. For example: hello.elf
Figure 14. Debug Configurations for Nios® V Processor—Main Tab.
- Under the Debugger tab, set these settings:
- Debug probe: Agilex SI/SoC Dev Kit (Name of the FPGA board/development kit)
- Transport type: JTAG
- JTAG frequency: 16 MHz
Figure 15. Debug Configurations for Nios® V Processor—Debugger Tab - Click Auto-detect Scan Chain to automatically detect JTAG scan chain information of the target device. Select the options from Device/Tap selection and Core selection.
- Based on the OS you use, configure the OS Awareness settings as follows:
- Intel HAL: No OS Awareness configuration is required.
- Other OS: Under the OS Awareness tab, turn on Enable OS Aware Debugging, and select the OS version applicable to you as listed below:
- OS: μC/OS-II and Version: 2.93.0
- OS: FreeRTOS and Version: 10.5.0
- OS: Zephyr and Version: 3.2.0
Note: Nios® V processor does not support Linux OS.
Figure 16. Enabling OS Aware Debugging in RISC-V Hardware Debugging - Click Debug. RiscFree* IDE for Intel® FPGAs downloads the program to the target and you can find the console prints as shown in the following diagram.
Figure 17. Console Prints after Debug Connection is Successful
- Refer to the Debugging Features with RiscFree IDE section for further debugging.
Note: You can issue a debug reset using niosv-download -r command. This command only resets the Nios® V processor if the debug reset interface is connected to the Nios® V processor IP's reset input in your Platform Designer.Note: niosv-download (under <Intel Quartus Prime installation directory>/niosv/bin directory) is only available for the Quartus® Prime software. This tool is not available for standalone RiscFree* IDE for Intel® FPGAsRiscFree IDE installation with the Quartus® Prime Programmer and Tools