Ashling* RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide

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ID 730783
Date 7/26/2024
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Document Table of Contents
Document Table of Contents x
1. About the RiscFree* IDE 2. Getting Started with the Ashling* RiscFree* IDE for Intel® FPGAs 3. Using Ashling* RiscFree* IDE for Intel® FPGAs with Nios® V Processor System 4. Using Ashling* RiscFree* IDE for Intel® FPGAs with Arm* Hard Processor System 5. Debugging Features with RiscFree* IDE for Intel® FPGAs 6. Debugging with Command-Line Interface 7. Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide Archives 8. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide A. Appendix
1. About the RiscFree* IDE x
1.1. Supported Devices 1.2. Quartus® Prime Software Support 1.3. Intel® Simics® Simulator for Intel® FPGAs Support
2. Getting Started with the Ashling* RiscFree* IDE for Intel® FPGAs x
2.1. Installing RiscFree* IDE for Intel FPGAs 2.2. Getting Started with RiscFree* IDE for Intel® FPGAs 2.3. Creating the Project 2.4. Building the Application 2.5. Run and Debug Configurations in the RiscFree* IDE for Intel® FPGAs 2.6. Debug Information in the RiscFree* IDE for Intel® FPGAs
2.1. Installing RiscFree* IDE for Intel FPGAs x
2.1.1. Bundled Installation with the Quartus® Prime Software 2.1.2. Standalone Installation
2.1.2. Standalone Installation x
2.1.2.1. Standalone Installation with Supported Quartus® Prime Software 2.1.2.2. Standalone Installation with the Quartus® Prime Programmer and Tools
2.2. Getting Started with RiscFree* IDE for Intel® FPGAs x
2.2.1. Ashling* RiscFree* IDE for Intel® FPGAs Workbench
2.2.1. Ashling* RiscFree* IDE for Intel® FPGAs Workbench x
2.2.1.1. Perspective, Editors, and Views 2.2.1.2. Starting a Project 2.2.1.3. Navigating the Project 2.2.1.4. Building the Project 2.2.1.5. Configuring the FPGA 2.2.1.6. Running the Project 2.2.1.7. Debugging the Project
2.3. Creating the Project x
2.3.1. Specifying the Project Location 2.3.2. Specifying the Project Name 2.3.3. Specifying the Project Type 2.3.4. Specifying the Configurations
2.5. Run and Debug Configurations in the RiscFree* IDE for Intel® FPGAs x
2.5.1. Opening the Run and Debug Configuration Dialog Boxes
2.6. Debug Information in the RiscFree* IDE for Intel® FPGAs x
2.6.1. Variables 2.6.2. Expressions 2.6.3. Registers 2.6.4. Memory 2.6.5. Disassembly
3. Using Ashling* RiscFree* IDE for Intel® FPGAs with Nios® V Processor System x
3.1. Importing Nios® V Processor Project 3.2. Building Nios® V Processor Project 3.3. Setting Run Configuration to Download Nios® V Processor Project 3.4. Setting Debug Configuration to Debug Nios® V Processor Project 3.5. Setting Debug Configuration to Debug a Booting Nios® V Processor Project 3.6. Debugging Tools
3.6. Debugging Tools x
3.6.1. View Variables 3.6.2. Adding Expressions 3.6.3. View Memory 3.6.4. Disassembly View with Registers View/ Stepping into assembler functions
4. Using Ashling* RiscFree* IDE for Intel® FPGAs with Arm* Hard Processor System x
4.1. Pre-requisite for Debugging Arm* HPS Project 4.2. Importing Arm* HPS Project 4.3. Setting Debug Configurations and Downloading Arm* HPS Project Using RiscFree* IDE
5. Debugging Features with RiscFree* IDE for Intel® FPGAs x
5.1. Debug Features in RiscFree* IDE 5.2. Processor System Debug 5.3. Heterogeneous Multicore Debug 5.4. Debugging µC/OS-II Application 5.5. Debugging FreeRTOS Application 5.6. Debugging Zephyr Application 5.7. Arm* HPS On-Chip Trace 5.8. Debugging the Arm* Linux Kernel 5.9. Debugging Target Software in an Intel® Simics Simulator Session
5.1. Debug Features in RiscFree* IDE x
5.1.1. Viewing Global Variables 5.1.2. Launching Memory Browser 5.1.3. Debugger Console 5.1.4. Specifying the SVD File 5.1.5. Breakpoint Settings 5.1.6. JTAG UART Output Terminal
5.2. Processor System Debug x
5.2.1. GUI for Debugging
5.3. Heterogeneous Multicore Debug x
5.3.1. Importing Nios® V Processor and Arm* HPS Projects 5.3.2. Setting Core Configuration
5.7. Arm* HPS On-Chip Trace x
5.7.1. Trace Bar 5.7.2. Trace View
5.8. Debugging the Arm* Linux Kernel x
5.8.1. Preparing Linux for Kernel Debugging 5.8.2. Debugging the Arm* HPS Linux Kernel
6. Debugging with Command-Line Interface x
6.1. Running Ashling* GBD Server 6.2. Running GDB 6.3. Nios® V Processor Example 6.4. ARM HPS Core Example
A. Appendix x
A.1. Optional Toolchain Configuration A.2. Performing External Tools Configuration A.3. Help Content A.4. Open-Source Components in RiscFree* IDE
A.1. Optional Toolchain Configuration x
A.1.1. Toolchain for Application and BSP A.1.2. Toolchain for Arm* Processor A.1.3. Modifying Toolchain Configuration
1. About the RiscFree* IDE
2. Getting Started with the Ashling* RiscFree* IDE for Intel® FPGAs
3. Using Ashling* RiscFree* IDE for Intel® FPGAs with Nios® V Processor System
4. Using Ashling* RiscFree* IDE for Intel® FPGAs with Arm* Hard Processor System
5. Debugging Features with RiscFree* IDE for Intel® FPGAs
6. Debugging with Command-Line Interface
7. Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide Archives
8. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide
A. Appendix

5.7. Arm* HPS On-Chip Trace

You can configure and capture the Arm HPS On-Chip Trace with Intel® FPGA Download Cable II. The following table shows the Arm* trace sources that generate instruction trace:
Table 10.  Arm Trace Source
Arm Trace Source Encoding Type Description Supported Device
Program Trace Macrocell (PTM) PTM A real-time trace module providing instruction tracing of a processor
  • Arria® 10
  • Intel® Cyclone® V
Embedded Trace Macrocell (ETM) ETMv4 The Arm trace source that captures data and instruction trace
  • Agilex® 7
  • Stratix® 10
Follow the steps to enable and configure the Trace feature:
  1. Launch Ashling Arm Hardware Debugging, and click the Trace tab.
    Figure 58. Trace Tab
  2. Click the Enable trace checkbox to enable the trace selected settings. The Trace architecture defaults to Arm Coresight. The trace selected settings appear in the following tab:
    1. Capture Settings
    2. Producer Settings
    3. Trigger/Filter Settings
      Figure 59. Capture Settings Sub-Tab
  3. Under the Capture Settings tab, set this settings:
    1. Select On-chip.
    2. Select one of the following Device Buffer Configuration:
      1. Embedded Trace FIFO (ETF) — stores trace data in small and fixed size trace buffer.
      2. Embedded Trace Router (ETR) — routes the trace data to the system memory. You need to specify the RAM location and Size .
    3. Wrap-around — enables overwriting old trace data with the new trace data when the trace buffer is full.
      Note: Wrap-around is optional. If you do not select Wrap-around, trace capture stops when the trace buffer is full.
  4. Under Producer Settings tab, set this settings:
    1. Select your preferred settings:
      1. Cycle Accurate Trace — captures trace on all cycles even if there is no trace to output on that cycle.
      2. Enable context ID — enables the tracing of the ASID and the current process ID.
      3. Enable timestamp — enables timestamps in your trace.
    2. For Encoding type, you can select ETMv4 or PTM. Refer to Table Arm Trace Source for more details.
      Note: ETMv3 is an older version of ETMv4 and not supported by Intel devices.
      Figure 60. Producer Settings Sub-tab
  5. Under Trigger/Filter Settings tab, click the Enable trigger checkbox.
    Figure 61. Trigger/Filter Settings Tab
  6. Click Add to bring up the Add Trigger dialog box as shown below:
    Figure 62. Add Trigger Dialog Box
    1. For Trace action, choose one of the following options:
      1. Trace include— limits trace to the selected address range
      2. Trace exclude— excludes trace from the selected address range
      3. Trace start point— starts tracing when the selected address is executed
      4. Trace stop point— stops tracing when the selected address is executed
    2. For Core, use the same core that you select in Debugger tab.
    3. For Access type, select the only available option — Instruction execution as instruction trace and to support trigger.
  7. Once you complete the configuration, click Debug.
  8. Open Trace view via Window > Show > View > Other > Debug > Trace. Click Fetch, decode and populate trace data button on the top right of the window to fetch trace data from the target and display in the Trace view as shown below.
    Figure 63. Trace View

Section Content
Trace Bar
Trace View

Level Two Title