Ashling* RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide

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ID 730783
Date 7/26/2024
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Document Table of Contents
Document Table of Contents x
1. About the RiscFree* IDE 2. Getting Started with the Ashling* RiscFree* IDE for Intel® FPGAs 3. Using Ashling* RiscFree* IDE for Intel® FPGAs with Nios® V Processor System 4. Using Ashling* RiscFree* IDE for Intel® FPGAs with Arm* Hard Processor System 5. Debugging Features with RiscFree* IDE for Intel® FPGAs 6. Debugging with Command-Line Interface 7. Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide Archives 8. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide A. Appendix
1. About the RiscFree* IDE x
1.1. Supported Devices 1.2. Quartus® Prime Software Support 1.3. Intel® Simics® Simulator for Intel® FPGAs Support
2. Getting Started with the Ashling* RiscFree* IDE for Intel® FPGAs x
2.1. Installing RiscFree* IDE for Intel FPGAs 2.2. Getting Started with RiscFree* IDE for Intel® FPGAs 2.3. Creating the Project 2.4. Building the Application 2.5. Run and Debug Configurations in the RiscFree* IDE for Intel® FPGAs 2.6. Debug Information in the RiscFree* IDE for Intel® FPGAs
2.1. Installing RiscFree* IDE for Intel FPGAs x
2.1.1. Bundled Installation with the Quartus® Prime Software 2.1.2. Standalone Installation
2.1.2. Standalone Installation x
2.1.2.1. Standalone Installation with Supported Quartus® Prime Software 2.1.2.2. Standalone Installation with the Quartus® Prime Programmer and Tools
2.2. Getting Started with RiscFree* IDE for Intel® FPGAs x
2.2.1. Ashling* RiscFree* IDE for Intel® FPGAs Workbench
2.2.1. Ashling* RiscFree* IDE for Intel® FPGAs Workbench x
2.2.1.1. Perspective, Editors, and Views 2.2.1.2. Starting a Project 2.2.1.3. Navigating the Project 2.2.1.4. Building the Project 2.2.1.5. Configuring the FPGA 2.2.1.6. Running the Project 2.2.1.7. Debugging the Project
2.3. Creating the Project x
2.3.1. Specifying the Project Location 2.3.2. Specifying the Project Name 2.3.3. Specifying the Project Type 2.3.4. Specifying the Configurations
2.5. Run and Debug Configurations in the RiscFree* IDE for Intel® FPGAs x
2.5.1. Opening the Run and Debug Configuration Dialog Boxes
2.6. Debug Information in the RiscFree* IDE for Intel® FPGAs x
2.6.1. Variables 2.6.2. Expressions 2.6.3. Registers 2.6.4. Memory 2.6.5. Disassembly
3. Using Ashling* RiscFree* IDE for Intel® FPGAs with Nios® V Processor System x
3.1. Importing Nios® V Processor Project 3.2. Building Nios® V Processor Project 3.3. Setting Run Configuration to Download Nios® V Processor Project 3.4. Setting Debug Configuration to Debug Nios® V Processor Project 3.5. Setting Debug Configuration to Debug a Booting Nios® V Processor Project 3.6. Debugging Tools
3.6. Debugging Tools x
3.6.1. View Variables 3.6.2. Adding Expressions 3.6.3. View Memory 3.6.4. Disassembly View with Registers View/ Stepping into assembler functions
4. Using Ashling* RiscFree* IDE for Intel® FPGAs with Arm* Hard Processor System x
4.1. Pre-requisite for Debugging Arm* HPS Project 4.2. Importing Arm* HPS Project 4.3. Setting Debug Configurations and Downloading Arm* HPS Project Using RiscFree* IDE
5. Debugging Features with RiscFree* IDE for Intel® FPGAs x
5.1. Debug Features in RiscFree* IDE 5.2. Processor System Debug 5.3. Heterogeneous Multicore Debug 5.4. Debugging µC/OS-II Application 5.5. Debugging FreeRTOS Application 5.6. Debugging Zephyr Application 5.7. Arm* HPS On-Chip Trace 5.8. Debugging the Arm* Linux Kernel 5.9. Debugging Target Software in an Intel® Simics Simulator Session
5.1. Debug Features in RiscFree* IDE x
5.1.1. Viewing Global Variables 5.1.2. Launching Memory Browser 5.1.3. Debugger Console 5.1.4. Specifying the SVD File 5.1.5. Breakpoint Settings 5.1.6. JTAG UART Output Terminal
5.2. Processor System Debug x
5.2.1. GUI for Debugging
5.3. Heterogeneous Multicore Debug x
5.3.1. Importing Nios® V Processor and Arm* HPS Projects 5.3.2. Setting Core Configuration
5.7. Arm* HPS On-Chip Trace x
5.7.1. Trace Bar 5.7.2. Trace View
5.8. Debugging the Arm* Linux Kernel x
5.8.1. Preparing Linux for Kernel Debugging 5.8.2. Debugging the Arm* HPS Linux Kernel
6. Debugging with Command-Line Interface x
6.1. Running Ashling* GBD Server 6.2. Running GDB 6.3. Nios® V Processor Example 6.4. ARM HPS Core Example
A. Appendix x
A.1. Optional Toolchain Configuration A.2. Performing External Tools Configuration A.3. Help Content A.4. Open-Source Components in RiscFree* IDE
A.1. Optional Toolchain Configuration x
A.1.1. Toolchain for Application and BSP A.1.2. Toolchain for Arm* Processor A.1.3. Modifying Toolchain Configuration
1. About the RiscFree* IDE
2. Getting Started with the Ashling* RiscFree* IDE for Intel® FPGAs
3. Using Ashling* RiscFree* IDE for Intel® FPGAs with Nios® V Processor System
4. Using Ashling* RiscFree* IDE for Intel® FPGAs with Arm* Hard Processor System
5. Debugging Features with RiscFree* IDE for Intel® FPGAs
6. Debugging with Command-Line Interface
7. Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide Archives
8. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide
A. Appendix

2.5.1. Opening the Run and Debug Configuration Dialog Boxes

You can open the run and debug configuration dialog boxes in two options:
  • Right-click an application, point to Run As, and click Run Configurations.
  • Right-click an application, point to Debug As, and click Debug Configurations.
Depending on which option you use, the dialog box title is either Run Configurations or Debug Configurations. However, both views show the same run configurations. Each run configuration appears on several tabs. The following table describes each tab.
Table 4.  Run (Debug) Configuration
Tab Description
Main
  • This tab allows you to specify the application project to run.
  • You can control the runtime parameters in the following ways:
    • Specify the name for the configuration
    • Specify the name of the project
    • Specify the path of the application
    • Select build configuration based on the location of the application
    Note: The RiscFree* IDE for Intel® FPGAs sets these parameters to reasonable defaults. Do not modify them unless you have a clear understanding of their effects.
Debugger
  • This tab allows you to control the connection between the host machine and the target hardware.
  • You can control the connection in the following ways:
    • Select the Debug Probe in the Debug Probe Configuration, if there is more than one debug probe available.
    • Click Auto-detect Scan Chain to detect JTAG scan chain information of the target device automatically.
    • Use GDB Server Setup to debug the software application remotely.
    • Use GDB Client Setup to communicate with the Ashling GDBServer via a TCP connection using GDB Remote Serial Protocol.
    • To modify GDB Server Setup and GDB Client Setup using the command line, you can refer to:
      • Running Ashling GBD Server for GDB Server Setup
      • Running GDB for GDB Client Setup
      Note: By default, the setup is generic. It can support all environments.
Startup

  • This tab allows you to configure options related to debugging your program. Example of the options are loading images or symbols and setting breakpoints, which help you analyze and troubleshoot your program during execution.

  • You can use load image and symbol specifically for booting.
    • If you want to download your program to analyze and troubleshoot your program during execution, turn on both load image and symbols.
    • If your program is in booting mode and you want to analyze and troubleshoot your program during execution, turn off both load image and symbols.
    Note: Nios® V processor supports hart ID of 0 only.
OS Awareness
This tab allows you to enable OS-aware debugging and specify the operating system to use to debug your design. The operating system are:
  • FreeRTOS
  • Linux,
  • Zephyr
  • μC/OS-II
You can also specify the location of the Python script for the RTOS.
Source

You can specify the location of source files that are used when running or debugging a C/C++ application. By default, the source files are taken from your project.

Common

When a run configuration is created, it is saved with the extension .launch. You can select an alternate place for storing your run configuration, how to access it, and which perspective to use while executing an application.

SVD Path

The RiscFree* IDE for Intel® FPGAs supports Device-specific System View Description (SVD) JSON format files. The files provide the peripheral registers viewer with detailed definitions. Typically, they are obtained via the CMSIS Packs or xPacks that have been installed. You can use ZIP to compress the file.

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