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Ixiasoft
Visible to Intel only — GUID: wcu1516336849595
Ixiasoft
1. Cyclone® V Hard Processor System Technical Reference Manual Revision History
Updated for: |
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Intel® Quartus® Prime Design Suite 21.2 |
Chapter | Date of Last Update |
---|---|
October 28, 2016 | |
Clock Manager | November 2, 2015 |
Reset Manager | November 2, 2015 |
FPGA Manager | June 14, 2019 |
System Manager | July 17, 2018 |
Scan Manager | May 3, 2016 |
System Interconnect | May 4, 2015 |
HPS-FPGA Bridges | September 3, 2020 |
Cortex®-A9 Microprocessor Unit Subsystem | September 3, 2020 |
CoreSight* Debug and Trace | July 31, 2014 |
SDRAM Controller Subsystem Controller | February 28, 2020 |
On-Chip Memory | January 26, 2018 |
NAND Flash Controller | August 28, 2023 |
SD/MMC Controller | July 8, 2021 |
Quad SPI Flash Controller | September 3, 2020 |
DMA Controller | January 26, 2018 |
Ethernet Media Access Controller | April 9, 2021 |
USB 2.0 OTG Controller | January 26, 2018 |
SPI Controller | January 26, 2018 |
I2C Controller | May 4, 2015 |
UART Controller | November 2, 2015 |
General-Purpose I/O Interface | September 3, 2020 |
Timer | June 30, 2014 |
Watchdog Timer | November 2, 2015 |
CAN Controller | November 2, 2015 |
Introduction to the HPS Component | December 30, 2013 |
Instantiating the HPS Component | November 2, 2015 |
HPS Component Interfaces | May 4, 2015 |
Simulating the HPS Component | May 3, 2016 |
Booting and Configuration | July 8, 2021 |
Document Version |
Changes |
---|---|
2016.10.28 |
|
2016.05.03 |
Maintenance release. |
2015.11.02 | Updated the link to the Memory Maps. |
2015.05.04 | Corrected the base address for NANDDATA in the "Peripheral Region Address Map" table. |
2014.12.15 | Maintenance release |
2014.07.31 | Updated address maps and register descriptions |
2014.06.30 | Maintenance release |
2014.02.28 | Maintenance release |
2013.12.30 | Maintenance release |
1.3 |
Minor updates. |
1.2 |
Updated address spaces section. |
1.1 |
Added peripheral region address map. |
1.0 |
Initial release. |
Document Version |
Changes |
---|---|
2020.01.13 | Correct typical sdmmc_clk frequencies in Flash Controller Clocks |
2015.11.02 | Minor formatting updates. |
2015.05.04 | Minor formatting updates. |
2014.12.15 | FREF, FVCO, and FOUT Equations section updated. More information added about vco register, M and N equations. Reference Clock information added to Clock Groups section. |
2014.06.30 | E0SC1 changed to HPS_CLK1 E0SC2 changed to HPS_CLK2 Added Address Map and Register Descriptions |
2014.02.28 | Updated content in the "Peripheral Clock Group" section |
2013.12.30 | Minor formatting updates. |
1.2 |
Minor updates. |
1.1 |
|
1.0 |
Initial release. |
Document Version |
Changes |
---|---|
2015.11.02 | Updated "Reset Pins" section |
2015.05.04 | Updated:
|
2014.12.15 |
|
2014.06.30 |
|
2014.02.28 | Updated sections:
|
2013.12.30 | Minor formatting issues. |
1.2 |
|
1.1 |
Added reset controller, functional description, and address map and register definitions sections. |
1.0 |
Initial release. |
Document Version |
Changes |
---|---|
2019.06.14 | Corrected the msel descriptions for encodings 0x0 through 0x2 and 0x4 to 0x6 in the stat register. |
2015.11.02 | Provided more information for the configuration schemes for the dedicated pins. |
2015.05.04 | Added information about FPPx32. |
2014.12.15 | Maintenance release |
2014.06.30 | Added address maps and register definitions |
2014.02.28 | Maintenance release |
2013.12.30 | Minor updates. |
1.3 |
Minor updates. |
1.2 |
Updated the FPGA configuration section. |
1.1 |
|
1.0 |
Initial release. |
Document Version |
Changes |
---|---|
2018.11.03 | Modified mode register bitfield descriptions for clarity. |
2018.07.17 | Made the following changes to the Pin Mux Control Group register block:
|
2014.06.30 |
|
2014.02.28 | Maintenance release |
2013.12.30 |
Maintenance release. |
1.2 |
Minor updates. |
1.1 |
Added functional description, address map and register definitions sections. |
1.0 |
Initial release. |
Document Version |
Changes |
---|---|
2016.05.03 | Added a list of the HPS I/O pins that do not support boundary scan tests in the Arm* JTAG-AP Scan Chains section. |
2015.11.02 | Maintenance release |
2015.05.04 | Maintenance release |
2014.12.15 | Maintenance release |
2014.06.30 | Add address map and register definitions |
2014.02.28 | Update to "Scan Manager Block Diagram and System Integration" section |
2013.12.30 |
Minor formatting issues |
1.2 |
Added JTAG-AP descriptions. |
1.1 |
Added block diagram and system integration, functional description, and address map and register definitions sections. |
1.0 |
Initial release. |
Document Version |
Changes |
---|---|
2015.05.04 |
|
2014.12.15 |
|
2014.06.30 |
|
2014.02.28 | Maintenance release |
2013.12.30 | Maintenance release |
1.2 |
Minor updates. |
1.1 |
|
1.0 |
Initial release. |
Document Version | Changes |
---|---|
2020.09.03 | Updated Taking HPS-FPGA Bridges Out of Reset with clarification on the state of the HPS GPIO during cold reset. |
2014.06.30 | Added address maps and register definitions |
2014.02.28 | Maintenance release |
2013.12.30 |
Maintenance release |
1.1 |
Described GPV |
1.0 |
Initial release |
Document Version |
Changes |
---|---|
2020.09.03 | Added Interconnect Master (L2M0) to the "HPS Peripheral Master Input IDs" table in HPS Peripheral Master Input IDs. |
2020.01.13 | Added new section Avoiding ACP Dependency Lockup |
2019.06.14 | Added details about arbitration behavior in the SCU when the ACP is not being used in the Implementation Details of the Snoop Control Unit section, |
2016.10.28 |
|
2016.05.03 | Maintenance release |
2015.11.02 |
|
2015.05.04 | Clarified EMAC0 and EMAC1 ACP Mapper IDs in the "HPS Peripheral Master Input IDs" table in the "HPS Peripheral Master Input IDs" section. |
2014.12.15 |
|
2014.06.30 |
|
2014.02.28 | Maintenance release |
2013.12.30 | Correct SDRAM region address in Arm* Cortex®-A9 MPCore* Address Map |
1.2 |
Minor updates. |
1.1 |
|
1.0 |
Initial release. |
Document Version |
Changes |
---|---|
2014.07.31 |
Updated the address map and register definitions. |
2014.06.30 |
Added address map and register definitions. |
2014.02.28 |
Maintenance release. |
2013.12.30 |
Maintenance release. |
1.2 |
Minor updates. |
1.1 |
Added functional description, programming model, and address map and register definition sections. |
1.0 |
Initial release. |
Document Version | Changes |
---|---|
2020.02.28 | In the Memory Protection section - Corrected the "Protection" field definition in the "Fields for Rules in Memory Protection Table". |
2018.07.17 | Modified text to clarify that there is support for up to 4 Gb external memory device per chip select. |
2015.11.02 |
|
2015.05.04 |
|
2014.12.15 |
|
2014.6.30 |
|
2013.12.30 |
|
1.1 | Added address map and register definitions section. |
1.0 | Initial release. |
Document Version |
Changes |
---|---|
2018.01.26 | Updated "On-Chip RAM Initialization" section with steps to enable ECC. |
2016.10.28 | Maintenance release |
2016.05.03 | Maintenance release |
2015.11.02 | Maintenance release |
2015.05.04 | Maintenance release |
2014.12.15 | Maintenance release |
2014.06.30 | Added address maps and register definitions |
2014.02.28 | Maintenance release |
2013.12.30 | Maintenance release |
1.1 |
Added address map section |
1.0 |
Initial release |
Document Version |
Changes |
---|---|
2023.08.28 | Added a note in the Timing Registers section. The note describes the NAND flash controller behavior in Boot mode and Performance mode. |
2022.11.14 | Updated to state that spare area is not ECC protected |
2018.01.26 | Updated "ECC Enabling" section with steps to enable ECC. |
2016.10.28 | Added content about the local memory buffer |
2016.05.27 | Added a link to the Supported Flash Devices for Cyclone V and Arria V SoC webpage. |
2016.05.03 | Maintenance release |
2015.11.02 |
|
2015.05.04 | Added information about clearing out the ECC before the feature is enabled |
2014.12.15 | Maintenance release |
2014.07.31 |
Updated address map and register definitions. |
2014.06.30 |
|
2014.02.28 | Maintenance release |
2013.12.30 | Maintenance release |
1.2 |
|
1.1 |
Added programming model section. |
1.0 |
Initial release |
Document Version | Changes |
---|---|
2021.07.08 | Changed the SD Card Clock Frequency in Changing the Card Clock Frequency. |
2021.05.07 | Corrected the Max Data Rate for MMCPlus and eMMC. |
2018.01.26 | Added "Enabling ECC" section. |
2017.12.27 | Added 8-bit support for eMMC in the "Features of SD/MMC Controller" section. (FB320076) |
2016.10.28 |
|
2016.05.27 | Added a link to the Supported Flash Devices for Cyclone V and Arria V SoC webpage. |
2016.05.03 | Maintenance release. |
2015.11.02 |
|
2015.05.04 | Added information about clearing out the ECC before the feature is enabled |
2014.12.15 | Maintenance release |
2014.06.30 | Added address maps and register definitions |
2014.02.28 | Maintenance release |
2013.12.30 | Maintenance release |
1.1 |
|
1.0 | Initial release. |
Document Version | Changes |
---|---|
2020.09.03 | Updated the definition for the QSPI register: indaddrtrig in the Quad SPI Flash Controller Address Map and Register Definitions section |
2019.07.09 | Maintenance release |
2019.06.14 |
|
2018.01.26 | Updated "Local Memory Buffer" section with steps to enable ECC. |
2016.10.28 | Maintenance release |
2016.05.27 |
|
2016.05.03 |
|
2015.11.02 |
|
2015.05.04 | Added information about clearing out the ECC before the feature is enabled |
2014.12.15 | Maintenance release |
2014.07.31 | Updated address maps and register descriptions |
2014.06.30 | Added address maps and register definitions |
2014.02.28 | Maintenance release |
2013.12.30 | Maintenance release |
1.2 | Minor updates. |
1.1 | Added block diagram and system integration, functional description, programming model, and address map and register definitions sections. |
1.0 | Initial release. |
Document Version |
Changes |
---|---|
2018.01.26 | Updated "Initializing and Clearing of Memory before Enabling ECC" section with steps to enable ECC. |
2016.10.28 | Maintenance release |
2016.05.03 | Maintenance release |
2015.11.02 |
|
2015.05.04 |
|
2014.12.15 | Maintenance release |
2014.07.31 | Updated address maps and register descriptions |
2014.06.30 | Added address maps and register definitions |
2014.02.28 | ECC updates |
1.2 |
Maintenance release |
1.1 |
Minor updates |
1.0 |
Initial release |
Document Version | Changes |
---|---|
2021.04.09 | Added emac_clk_tx_i handling requirement for exported HPS EMAC GMII interface in the EMAC FPGA Interface Initialization section. |
2020.08.18 | Updated EMAC HPS Interface Initialization to clarify how to verify RX PHY clocks after bringing the Ethernet PHY out of reset. |
2019.06.14 | Claified the PCF bit description for encoding value 0x2 in the MAC_Frame_Filter register.
|
2016.10.28 |
|
2016.05.03 | Maintenance release. |
2015.11.02 |
|
2015.05.04 |
|
2014.12.15 |
|
2014.06.30 | Updated EMAC to RGMII Interface table with EMAC Port names Updated EMAC to FPGA PHY Interface table with Signal names Updated EMAC to FPGA IEEE1588 Timestamp Interface with Signal names Added Address Map and Register Descriptions |
2014.02.28 | ECC updates. |
1.4 | Maintenance release. |
1.3 |
|
1.2 | Updated the HPS boot and FPGA configuration sections. |
Document Version |
Changes |
---|---|
2018.01.26 | Added steps for enabling ECC. |
2016.10.28 | Maintenance release. |
2016.05.03 | Maintenance release. |
2015.11.02 | Renamed "ULPI PHY Interface" section to "USB 2.0 ULPI PHY Signal Description" and moved it after the "USB OTG Controller Block Diagram and System Integration" section. |
2015.05.04 | Maintenance release. |
2014.12.15 |
|
2014.07.31 |
Updated address map and register definitions. |
2014.06.30 |
Added USB OTG Controller address map and register definitions. |
2014.02.28 |
Maintenance release. |
2013.12.30 |
Maintenance release. |
1.2 |
|
1.1 |
Added information about ECCs. |
1.0 |
Initial release. |
Document Version |
Changes |
---|---|
2017.01.26 | Corrected the support information for continuous data transfers in SPI Serial Format. |
2016.10.28 | Maintenance release. |
2016.05.03 | Maintenance release. |
2015.11.02 |
|
2015.05.04 | Maintenance release. |
2014.12.15 |
|
2014.06.30 |
|
2014.02.28 | Maintenance release. |
2013.12.30 | Minor formatting updates. |
1.2 |
Minor updates. |
1.1 |
Added programming model, address map and register definitions, clocks, and reset sections. |
1.0 |
Initial release. |
Document Version |
Changes |
---|---|
2015.05.04 |
|
2014.12.15 |
|
2014.06.30 | HPS I2C Signals for FPGA Routing table updated I2C interface in FPGA Fabric diagram added Added Address Map and Register Descriptions |
2014.02.28 | Maintenance release. |
2013.12.30 | Added HPS I2c Signals for FPGA routing to "Interface Pins" section. |
1.2 |
Minor updates. |
1.1 |
Added programming model, address map and register definitions, clocks, reset, and interface pins sections. |
1.0 |
Initial release. |
Document Version |
Changes |
---|---|
2015.11.02 | Renamed Interface Pins section to HPS I/O Pins and moved this section and FPGA Routing under UART Controller Signal Description |
2015.05.04 | Maintenance release. |
2014.12.15 |
|
2014.06.30 |
|
2014.02.28 | Maintenance release |
2013.12.30 | Minor formatting updates. |
1.2 |
Minor updates. |
1.1 |
Added programming model, address map and register definitions, and reset sections. |
1.0 |
Initial release. |
Document Version |
Changes |
---|---|
2020.09.03 | Added information about the state of HPS GPIO during cold reset in the Taking the GPIO Interface Out of Reset section. |
2019.06.14 | Added GPIO State During Reset section. |
2014.12.15 |
|
2014.06.30 | Added Address Map and Register Descriptions |
2014.02.28 | Updated content in sections:
|
2013.12.30 | Minor formatting updates Updated GPIO interface block diagram and GPIO interface pin table |
1.2 |
Minor updates. |
1.1 |
Added programming model section. |
1.0 |
Initial release. |
Document Version |
Changes |
---|---|
2014.06.30 |
|
2014.02.28 | Maintenance release. |
2013.12.30 | Minor formatting updates. |
1.2 |
Minor updates. |
1.1 |
Added programming model and address map and register definitions sections. |
1.0 |
Initial release. |
Document Version |
Changes |
---|---|
2015.11.02 | Added note to "Watchdog Timer Counter" section. |
2015.05.04 | Maintenance release. |
2014.12.15 |
|
2014.06.30 |
|
2014.02.28 | Maintenance release. |
2013.12.30 | Minor formatting updates. |
1.2 |
Minor updates. |
1.1 |
Added programming model and address map and register definitions sections. |
1.0 |
Initial release. |
Document Version |
Changes |
---|---|
2015.11.02 | Updated "CAN Message Transfer" section. |
2015.05.04 | Maintenance release. |
2014.12.15 |
|
2014.06.30 | Add address map and register definitions |
2014.02.28 | Maintenance release |
2013.12.30 | Minor formatting updates |
1.2 |
|
1.1 |
Added block diagram and system integration, functional description, programming model, and address map and register definitions sections. |
1.0 |
Initial release. |
Document Version | Changes |
---|---|
2013.12.30 | Maintenance release |
1.0 |
Maintenance release. |
0.1 |
Preliminary draft. |
Document Version |
Changes |
---|---|
2015.11.02 | Updated Sections:
|
2015.05.04 | Maintenance release. |
2014.12.15 | Maintenance release. |
2014.02.28 |
|
1.2 |
Maintenance release. |
1.1 |
|
1.0 |
Initial release. |
0.1 |
Preliminary draft. |
Document Version |
Changes |
---|---|
2015.05.04 |
|
2014.12.15 | User Clock 2 has been removed |
2014.06.30 | Added address map and register descriptions |
2014.02.28 | Added sections:
Removed section:
Updated sections:
|
2013.12.30 | Minor formatting issues |
1.1 |
|
1.0 |
Initial release. |
0.1 |
Preliminary draft. |
Document Version |
Changes |
---|---|
2016.05.03 | Removed references to FPGA to HPS SDRAM simulation. |
2015.11.02 | Maintenance release |
2015.05.04 | Maintenance release |
2014.12.15 | Maintenance release |
2014.11.14 |
|
2014.02.28 | Added new sections:
Updated content in sections:
|
2013.12.30 | Maintenance release |
1.1 |
|
1.0 |
Initial release. |
0.1 |
Preliminary draft. |
Document Version |
Changes |
---|---|
2021.07.08 | Added information about HPS independent power in Booting and Configuration Options. |
2020.09.03 | Added information about where the HPS IO Configuration is contained in the Typical Preloader Boot Flow section. |
2018.07.17 |
|
2016.05.27 | Changed the name of the internal QSPI reference clock from qspi_clk to qspi_ref_clk; and the external QSPI output clock, from sclk_out to qspi_clk. |
2016.05.03 |
|
2015.11.02 | Maintenance Release |
2015.05.04 |
|
2014.12.15 |
|
2014.06.30 | Maintenance release |
2014.02.28 | Correction to "Leading the Preloader" section |
2013.12.30 |
|
1.3 |
|
1.2 |
Updated the HPS boot and FPGA configuration sections. |
1.1 |
|
1.0 |
Initial release. |