Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

1. Cyclone® V Hard Processor System Technical Reference Manual Revision History

Updated for:
Intel® Quartus® Prime Design Suite 21.2
Table 1.   Cyclone® V Hard Processor System Technical Reference Manual Revision History Summary
Chapter Date of Last Update

Introduction to the Hard Processor System

October 28, 2016
Clock Manager November 2, 2015
Reset Manager November 2, 2015
FPGA Manager June 14, 2019
System Manager July 17, 2018
Scan Manager May 3, 2016
System Interconnect May 4, 2015
HPS-FPGA Bridges September 3, 2020
Cortex®-A9 Microprocessor Unit Subsystem September 3, 2020
CoreSight* Debug and Trace July 31, 2014
SDRAM Controller Subsystem Controller February 28, 2020
On-Chip Memory January 26, 2018
NAND Flash Controller August 28, 2023
SD/MMC Controller July 8, 2021
Quad SPI Flash Controller September 3, 2020
DMA Controller January 26, 2018
Ethernet Media Access Controller April 9, 2021
USB 2.0 OTG Controller January 26, 2018
SPI Controller January 26, 2018
I2C Controller May 4, 2015
UART Controller November 2, 2015
General-Purpose I/O Interface September 3, 2020
Timer June 30, 2014
Watchdog Timer November 2, 2015
CAN Controller November 2, 2015
Introduction to the HPS Component December 30, 2013
Instantiating the HPS Component November 2, 2015
HPS Component Interfaces May 4, 2015
Simulating the HPS Component May 3, 2016
Booting and Configuration July 8, 2021

Document Version

Changes

2016.10.28
  • Added 8-bit support for eMMC for SD/MMC
  • Renamed MPU Subsystem to Cortex®-A9 MPCore*

2016.05.03

Maintenance release.
2015.11.02 Updated the link to the Memory Maps.
2015.05.04 Corrected the base address for NANDDATA in the "Peripheral Region Address Map" table.
2014.12.15 Maintenance release
2014.07.31 Updated address maps and register descriptions
2014.06.30 Maintenance release
2014.02.28 Maintenance release
2013.12.30 Maintenance release

1.3

Minor updates.

1.2

Updated address spaces section.

1.1

Added peripheral region address map.

1.0

Initial release.

Introduction to the Hard Processor System

Document Version

Changes

2020.01.13 Correct typical sdmmc_clk frequencies in Flash Controller Clocks
2015.11.02 Minor formatting updates.
2015.05.04 Minor formatting updates.
2014.12.15

FREF, FVCO, and FOUT Equations section updated. More information added about vco register, M and N equations.

Reference Clock information added to Clock Groups section.

2014.06.30

E0SC1 changed to HPS_CLK1

E0SC2 changed to HPS_CLK2

Added Address Map and Register Descriptions

2014.02.28

Updated content in the "Peripheral Clock Group" section

2013.12.30

Minor formatting updates.

1.2

Minor updates.

1.1

  • Reorganized and expanded functional description section.
  • Added address map and register definitions section.

1.0

Initial release.

Clock Manager

Document Version

Changes

2015.11.02 Updated "Reset Pins" section
2015.05.04 Updated:
  • MISC Group, Generated Module Resets table
  • "Reset Pins" section
2014.12.15
  • Signal power information added to "HPS External Reset Sources" section
  • Updated block diagram with h2f_dbg_rst_n signal
2014.06.30
  • Updated "Functional Description of Reset Manager"
  • Added address map and register descriptions
2014.02.28

Updated sections:

  • Reset Sequencing
  • Warm Reset Assertion Sequence
2013.12.30

Minor formatting issues.

1.2

  • Added cold and warm reset timing diagrams.

1.1

Added reset controller, functional description, and address map and register definitions sections.

1.0

Initial release.

Reset Manager

Document Version

Changes

2019.06.14 Corrected the msel descriptions for encodings 0x0 through 0x2 and 0x4 to 0x6 in the stat register.
2015.11.02 Provided more information for the configuration schemes for the dedicated pins.
2015.05.04 Added information about FPPx32.
2014.12.15 Maintenance release
2014.06.30 Added address maps and register definitions
2014.02.28 Maintenance release
2013.12.30 Minor updates.

1.3

Minor updates.

1.2

Updated the FPGA configuration section.

1.1

  • Updated the configuration schemes table.
  • Updated the FPGA configuration section.
  • Added address map and register definitions section.

1.0

Initial release.

FPGA Manager

Document Version

Changes

2018.11.03 Modified mode register bitfield descriptions for clarity.
2018.07.17 Made the following changes to the Pin Mux Control Group register block:
  • Removed MIXED2_IO0 through MIXED2_IO7 and added MIXED1_IO0 through MIXED1_IO7.
  • Added note to MIXED1_IO21 to indicate that it does not apply to the F484 package.
  • Added new registers in the Pin Mux Control Group for routing QSPI, SD/MMC, UART, I2C, CAN, and SPI signals to the FPGA.
2014.06.30
  • Added address map and register descriptions
  • Updated ECC Parity Control
  • CAN controller section added
2014.02.28 Maintenance release

2013.12.30

Maintenance release.

1.2

Minor updates.

1.1

Added functional description, address map and register definitions sections.

1.0

Initial release.

System Manager

Document Version

Changes

2016.05.03 Added a list of the HPS I/O pins that do not support boundary scan tests in the Arm* JTAG-AP Scan Chains section.
2015.11.02 Maintenance release
2015.05.04 Maintenance release
2014.12.15 Maintenance release
2014.06.30

Add address map and register definitions

2014.02.28 Update to "Scan Manager Block Diagram and System Integration" section

2013.12.30

Minor formatting issues

1.2

Added JTAG-AP descriptions.

1.1

Added block diagram and system integration, functional description, and address map and register definitions sections.

1.0

Initial release.

Scan Manager

Document Version

Changes

2015.05.04
  • Reference AXI ID encoding in MPU chapter
  • Add information about the SDRAM address space
2014.12.15
  • Minor correction to table in "Available Address Maps"
  • Add detail to "L3 Address Space"
2014.06.30
  • Corrected master interconnect security properties for:
    • Ethernet MAC
    • ETR
  • Added address map and register descriptions
2014.02.28 Maintenance release
2013.12.30 Maintenance release

1.2

Minor updates.

1.1

  • Added interconnect connectivity matrix.
  • Rearranged functional description sections.
  • Simplified address remapping section.
  • Added address map and register definitions section.

1.0

Initial release.

System Interconnect
Document Version Changes
2020.09.03 Updated Taking HPS-FPGA Bridges Out of Reset with clarification on the state of the HPS GPIO during cold reset.
2014.06.30 Added address maps and register definitions
2014.02.28 Maintenance release

2013.12.30

Maintenance release

1.1

Described GPV

1.0

Initial release

HPS-FPGA Bridges

Document Version

Changes

2020.09.03 Added Interconnect Master (L2M0) to the "HPS Peripheral Master Input IDs" table in HPS Peripheral Master Input IDs.
2020.01.13 Added new section Avoiding ACP Dependency Lockup
2019.06.14 Added details about arbitration behavior in the SCU when the ACP is not being used in the Implementation Details of the Snoop Control Unit section,
2016.10.28
  • Added note to "AXI Master Configuration for ACP Access" section
  • Added "Configuring AxCACHE[3:0] Sideband Signals" and "Configuring AxUser[4:0] Sideband Signals" subsections to the "AXI Master Configuration for ACP Access" section
  • Added note in the "Implementation Details" subsection of the "ACP ID Mapper" section.
2016.05.03 Maintenance release
2015.11.02
  • Reordered "L2 Cache" subsections
  • Renamed "ECC Support" L2 subsection to be "Single Event Upset Protection"
  • Added "L2 Cache Parity" subsection in "L2 Cache" section
2015.05.04 Clarified EMAC0 and EMAC1 ACP Mapper IDs in the "HPS Peripheral Master Input IDs" table in the "HPS Peripheral Master Input IDs" section.
2014.12.15
  • Added bus transaction scenarios in the "Accelerator Coherency Port" section
  • Added the "AxUSER and AxCACHE Attributes" subsection to the "Accelerator Coherency Port" section
  • Added the "Shared Requests on ACP" subsection to the "Accelerator Coherency Port" section
  • Added the "Configuration for ACP Use" subsection to the "Accelerator Coherency Port" section
  • Clarified how to use fixed mapping mode in the ACP ID Mapper
  • Updated HPS Peripheral Master Input IDs table
  • Added a note to the "Control of the AXI User Sideband Signals" subsection in the "ACP ID Mapper" section.
  • Added parity error handling information to the "L1 Caches" section and the "Cache Controller Configuration" topic of the "L2 Cache" section.
2014.06.30
  • Added Reset Section to Cortex®-A9 Processor
  • Updated HPS Peripheral Master Input IDs table
  • Added ACP ID Mapper Address Map and Register Definitions
  • Added information in ECC Support section regarding ECC errors
  • Minor clarifications regarding MPU description and module revision numbers
2014.02.28 Maintenance release
2013.12.30

Correct SDRAM region address in Arm* Cortex®-A9 MPCore* Address Map

1.2

Minor updates.

1.1

  • Add description of the ACP ID mapper
  • Consolidate redundant information

1.0

Initial release.

Cortex-A9 Microprocessor Unit Subsystem

Document Version

Changes

2014.07.31

Updated the address map and register definitions.

2014.06.30

Added address map and register definitions.

2014.02.28

Maintenance release.

2013.12.30

Maintenance release.

1.2

Minor updates.

1.1

Added functional description, programming model, and address map and register definition sections.

1.0

Initial release.

CoreSight Debug and Trace
Document Version Changes
2020.02.28 In the Memory Protection section - Corrected the "Protection" field definition in the "Fields for Rules in Memory Protection Table".
2018.07.17 Modified text to clarify that there is support for up to 4 Gb external memory device per chip select.
2015.11.02
  • Added information regarding calculation of ECC error byte address location from erraddr register in "User Notification of ECC Errors" section
  • Added information regarding bus response to memory protection transaction failure in "Memory Protection" section
  • Clarified "Protection" row in "Fields for Rules in Memory Protection" table in the "Memory Protection" section
  • Clarified protruledata.security column in "Rules in Memory Protection Table for Example Configuration" table in the "Example of Configuration for TrustZone" section
  • Added note about double-bit error functionality in "ECC Write Backs" subsection of "ECC" section
  • Added the "DDR Calibration" subsection under "DDR PHY" section
2015.05.04
  • Added the recommended sequence for writing or reading a rule in the "Memory Protection" section.
2014.12.15
  • Added SDRAM Protection Access Flow Diagram to "Memory Protection" subsection in the "Single-Port Controller Operation" section.
  • Changed the "SDRAM Multi-Port Scheduling" section to "SDRAM Multi-Port Arbitration" and added detailed information on how to use and program the priority and weighted arbitration scheme.
2014.6.30
  • Added Port Mappings section.
  • Added SDRAM Controller Memory Options section.
  • Enhanced Example of Configuration for TrustZone section.
  • Added SDRAM Controller address map and registers.
2013.12.30
  • Added Generating a Preloader Image for HPS with EMIF section.
  • Added Debugging HPS SDRAM in the Preloader section.
  • Enhanced Simulation section.
1.1 Added address map and register definitions section.
1.0 Initial release.
SDRAM Controller Subsystem

Document Version

Changes

2018.01.26 Updated "On-Chip RAM Initialization" section with steps to enable ECC.
2016.10.28 Maintenance release
2016.05.03 Maintenance release
2015.11.02 Maintenance release
2015.05.04 Maintenance release
2014.12.15 Maintenance release
2014.06.30 Added address maps and register definitions
2014.02.28 Maintenance release
2013.12.30 Maintenance release

1.1

Added address map section

1.0

Initial release

On-Chip Memory

Document Version

Changes

2023.08.28 Added a note in the Timing Registers section. The note describes the NAND flash controller behavior in Boot mode and Performance mode.
2022.11.14 Updated to state that spare area is not ECC protected
2018.01.26 Updated "ECC Enabling" section with steps to enable ECC.
2016.10.28 Added content about the local memory buffer
2016.05.27 Added a link to the Supported Flash Devices for Cyclone V and Arria V SoC webpage.
2016.05.03 Maintenance release
2015.11.02
  • Moved "Interface Signals" section after "NAND Flash Controller Block Diagram and System Integration" section and renamed it to "NAND Flash Controller Signal Description"
  • Updated the Interrupt and DMA Enabling section to recommend reading back a register to ensure clearing an interrupt status
  • Specified the valid values for Burst Length in the Command-Data Pair 4 table
  • Updated the description of dma_cmd_comp and added a RESERVED bit for intr_status0/1/2/3 and intr_en0/1/2/3
2015.05.04 Added information about clearing out the ECC before the feature is enabled
2014.12.15 Maintenance release

2014.07.31

Updated address map and register definitions.

2014.06.30

  • Added address map and register definitions.
  • Removed Command DMA section.
2014.02.28 Maintenance release
2013.12.30 Maintenance release

1.2

  • Supports one 8‑bit device
  • Show additional supported block sizes
  • Bad block marker handling

1.1

Added programming model section.

1.0

Initial release

NAND Flash Controller
Document Version Changes
2021.07.08 Changed the SD Card Clock Frequency in Changing the Card Clock Frequency.
2021.05.07 Corrected the Max Data Rate for MMCPlus and eMMC.
2018.01.26 Added "Enabling ECC" section.
2017.12.27 Added 8-bit support for eMMC in the "Features of SD/MMC Controller" section. (FB320076)
2016.10.28
  • Removed SPI support in tables in the Features section
  • Added 8-bit support for eMMC for SD/MMC
2016.05.27 Added a link to the Supported Flash Devices for Cyclone V and Arria V SoC webpage.
2016.05.03 Maintenance release.
2015.11.02
  • Moved "Interface Signals" section below "SD/MMC Controller Block Diagram and System Integration" section and renamed to "SD/MMC Signal Description." Clarified signals in this section.
  • Added information that Card Detect is only supported on interfaces routed via the FPGA fabric.
2015.05.04 Added information about clearing out the ECC before the feature is enabled
2014.12.15 Maintenance release
2014.06.30 Added address maps and register definitions
2014.02.28 Maintenance release
2013.12.30 Maintenance release
1.1
  • Added programming model section.
  • Reorganized programming information.
  • Added information about ECCs.
  • Added pin listing.
  • Updated clocks section.
1.0 Initial release.
SD/MMC Controller
Document Version Changes
2020.09.03 Updated the definition for the QSPI register: indaddrtrig in the Quad SPI Flash Controller Address Map and Register Definitions section
2019.07.09

Maintenance release

2019.06.14
  • Added a new section, Write Request, with WREN and RDSR information
  • Removed step 6 in Indirect Write Operation with DMA Disabled because it is unnecessary when DMA is disabled.
2018.01.26 Updated "Local Memory Buffer" section with steps to enable ECC.
2016.10.28 Maintenance release
2016.05.27
  • Changed the name of the internal QSPI reference clock from qspi_clk to qspi_ref_clk; and the external QSPI output clock, from sclk_out to qspi_clk.
  • Added a link to the Supported Flash Devices for Cyclone V and Arria V SoC webpage.
  • Re-worded information about disabling the watermark feature in the "Indirect Read Operation" and "Indirect Write Operation" sections.
2016.05.03
  • Added clarification for the SRAM indirect read and write size allocations.
  • Updated the SRAM block on the "Quad SPI Flash Controller Block Diagram and System Integration" figure.
2015.11.02
  • Moved "Interface Signals" section below "Quad SPI Flash Controller Block Diagram and System Integration"
  • Better defined l4_mp_clk clock.
  • Updated step 11 in the "Setting Up the Quad SPI Flash Controller" for clarity.
2015.05.04 Added information about clearing out the ECC before the feature is enabled
2014.12.15 Maintenance release
2014.07.31 Updated address maps and register descriptions
2014.06.30

Added address maps and register definitions

2014.02.28 Maintenance release
2013.12.30 Maintenance release
1.2 Minor updates.
1.1 Added block diagram and system integration, functional description, programming model, and address map and register definitions sections.
1.0 Initial release.
Quad SPI Flash Controller

Document Version

Changes

2018.01.26 Updated "Initializing and Clearing of Memory before Enabling ECC" section with steps to enable ECC.
2016.10.28 Maintenance release
2016.05.03 Maintenance release
2015.11.02
  • Updated link point to the HPS Address Map and Register Definitions
  • Added information about the instruction fetch cache properties
  • Added a description about the relationship between the GIC interrupt map and INTCLR register
2015.05.04
  • Added Synopsys* handshake rules.
  • Added information about the Bosch* CAN protocol.
2014.12.15 Maintenance release
2014.07.31 Updated address maps and register descriptions
2014.06.30 Added address maps and register definitions
2014.02.28

ECC updates

1.2

Maintenance release

1.1

Minor updates

1.0

Initial release

DMA Controller
Document Version Changes
2021.04.09 Added emac_clk_tx_i handling requirement for exported HPS EMAC GMII interface in the EMAC FPGA Interface Initialization section.
2020.08.18 Updated EMAC HPS Interface Initialization to clarify how to verify RX PHY clocks after bringing the Ethernet PHY out of reset.
2019.06.14 Claified the PCF bit description for encoding value 0x2 in the MAC_Frame_Filter register.
  • Clarified "Busy Bit" (gb bit of GMII_Address register) in Flow_Control register description.
  • Clarified that ttc bit resides in the Operation_Mode Register (Register 6).
  • Clarified that the pcsancis and the pcslchgis bits of theInterrupt_Status register can be ignored because they apply to TBI, RTBI, or SGMII interface only.
2016.10.28
  • Note added into PHY Interface section
  • Bit 16 updated Transmit Descriptor table
2016.05.03 Maintenance release.
2015.11.02
  • Added the following subsections in the "Layer 3 and Layer 4 Filters" section:
    • Layer 3 and Layer 4 Filters Register Set
    • Layer 3 Filtering
    • Layer 4 Filtering
2015.05.04
  • Corrected IEEE 1588 timestamp resolution in the "EMAC Block Diagram and System Integration" section and the "IEEE 1588-2002 Timestamps" section
  • Added reset pulse width for rst_clk_tx_n_o and rst_clk_rx_n_o in the "FPGA EMAC I/O signals" section
  • Added subsections "Ordinary Clock," "Boundary Clock," "End-to-End Transparent Clock" and "Peer-to-Peer Transparent Clock" in the "Clock Type" section
2014.12.15
  • Updated EMAC Block Diagram and System Integration section with new diagram and information.
  • Added Signal Descriptions section.
  • Added EMAC Internal Interfaces section.
  • Added TX FIFO and RX FIFO subsection to the Transmit and Receive Data FIFO Buffers section.
  • Updated Descriptor Overview section to clarify support for only enhanced (alternate) descriptors.
  • Added Destination and Source Address Filtering Summary in Frame Filtering Section.
  • Added Clock Structure sub-section to Clocks and Resets section
  • Added System Level EMAC Configuration Registers section in Ethernet Programming Model
  • Added EMAC Interface Initialization for FPGA GMII/MII Mode section in Ethernet Programming Model
  • Added EMAC Interface Initialization for RGMII/RMII Mode section in Ethernet Programming Model
  • Corrected DMA Initialization and EMAC Initialization and Configuration titles to appear on correct initialization information
  • Removed duplicate programming information for DMA
  • Added Taking the Ethernet MAC Out of Reset section.
2014.06.30

Updated EMAC to RGMII Interface table with EMAC Port names

Updated EMAC to FPGA PHY Interface table with Signal names

Updated EMAC to FPGA IEEE1588 Timestamp Interface with Signal names

Added Address Map and Register Descriptions

2014.02.28 ECC updates.
1.4 Maintenance release.
1.3
  • Expanded shared memory block table.
  • Added CSEL tables.
  • Additional minor updates.
1.2 Updated the HPS boot and FPGA configuration sections.
Ethernet Media Access Controller

Document Version

Changes

2018.01.26 Added steps for enabling ECC.
2016.10.28 Maintenance release.
2016.05.03 Maintenance release.
2015.11.02 Renamed "ULPI PHY Interface" section to "USB 2.0 ULPI PHY Signal Description" and moved it after the "USB OTG Controller Block Diagram and System Integration" section.
2015.05.04 Maintenance release.
2014.12.15
  • Maintenance release.
  • Added Taking the USB OTG Out of Reset section.

2014.07.31

Updated address map and register definitions.

2014.06.30

Added USB OTG Controller address map and register definitions.

2014.02.28

Maintenance release.

2013.12.30

Maintenance release.

1.2

  • Described interrupt generation.
  • Described software initialization in host and device modes.
  • Described software operation in host and device modes.
  • Simplified features list.
  • Simplified hardware description.

1.1

Added information about ECCs.

1.0

Initial release.

USB 2.0 OTG Controller

Document Version

Changes

2017.01.26 Corrected the support information for continuous data transfers in SPI Serial Format.
2016.10.28 Maintenance release.
2016.05.03 Maintenance release.
2015.11.02
  • Renamed "Interface Pins" section to "Interface to HPS I/O" and moved it under the "SPI Controller Signal Description" section
  • Moved "FPGA Routing" section under "SPI Controller Signal Description" section
  • Added Multi-Master mode to "Features of the SPI Controller" section
  • Updated "RXD Sample Delay" section
  • Updated "SPI Slave" section
  • Updated "Glue Logic for Master Port ss_in_n" section
2015.05.04 Maintenance release.
2014.12.15
  • Maintenance release.
  • Added Taking the SPI Out of Reset section.
2014.06.30
  • "Glue Logic for Master Port ss_in_n" section added
  • Interface Pins topic added
  • FPGA Routing topic added
  • Added address aap and register descriptions
2014.02.28 Maintenance release.
2013.12.30

Minor formatting updates.

1.2

Minor updates.

1.1

Added programming model, address map and register definitions, clocks, and reset sections.

1.0

Initial release.

SPI Controller

Document Version

Changes

2015.05.04
  • Added Impact of SCL Rise Time and Fall Time On Generated SCL figure to "Clock Synchronization" section
  • Updated "Minimum High and Low Counts" section
2014.12.15
  • Maintenance release.
  • Added Taking the I2C Out of Reset section.
2014.06.30

HPS I2C Signals for FPGA Routing table updated

I2C interface in FPGA Fabric diagram added

Added Address Map and Register Descriptions

2014.02.28 Maintenance release.
2013.12.30

Added HPS I2c Signals for FPGA routing to "Interface Pins" section.

1.2

Minor updates.

1.1

Added programming model, address map and register definitions, clocks, reset, and interface pins sections.

1.0

Initial release.

I2C Controller

Document Version

Changes

2015.11.02 Renamed Interface Pins section to HPS I/O Pins and moved this section and FPGA Routing under UART Controller Signal Description
2015.05.04 Maintenance release.
2014.12.15
  • Maintenance release.
  • Added Taking the UART Out of Reset section.
2014.06.30
  • UART(RS232) Serial Protocol topic added
  • Interrupts section updated
  • Updated Interrupt type table
  • Added address map and register descriptions
2014.02.28 Maintenance release
2013.12.30

Minor formatting updates.

1.2

Minor updates.

1.1

Added programming model, address map and register definitions, and reset sections.

1.0

Initial release.

UART Controller

Document Version

Changes

2020.09.03 Added information about the state of HPS GPIO during cold reset in the Taking the GPIO Interface Out of Reset section.
2019.06.14 Added GPIO State During Reset section.
2014.12.15
  • Maintenance release.
  • Added Taking the GPIO Out of Reset section.
2014.06.30

Added Address Map and Register Descriptions

2014.02.28

Updated content in sections:

  • Features of the GPIO Interface
  • GPIO Interface Block Diagram and System Integration
  • Debounce Operation
2013.12.30

Minor formatting updates

Updated GPIO interface block diagram and GPIO interface pin table

1.2

Minor updates.

1.1

Added programming model section.

1.0

Initial release.

General-Purpose I/O Interface

Document Version

Changes

2014.06.30
  • "FPGA Interface" section added
  • Added address map and register descriptions
2014.02.28 Maintenance release.
2013.12.30

Minor formatting updates.

1.2

Minor updates.

1.1

Added programming model and address map and register definitions sections.

1.0

Initial release.

Timer

Document Version

Changes

2015.11.02 Added note to "Watchdog Timer Counter" section.
2015.05.04 Maintenance release.
2014.12.15
  • Maintenance release.
  • Added "Taking the Watchdog Timer Out of Reset" section.
2014.06.30
  • "FPGA Interface" section added
  • Added address map and register descriptions
2014.02.28 Maintenance release.
2013.12.30

Minor formatting updates.

1.2

Minor updates.

1.1

Added programming model and address map and register definitions sections.

1.0

Initial release.

Watchdog Timer

Document Version

Changes

2015.11.02 Updated "CAN Message Transfer" section.
2015.05.04 Maintenance release.
2014.12.15
  • Maintenance release.
  • Added Taking the CAN Controller Out of Reset section.
2014.06.30 Add address map and register definitions
2014.02.28 Maintenance release
2013.12.30

Minor formatting updates

1.2

  • Minor updates.
  • Expanded reset section.
  • Expanded interrupts section.

1.1

Added block diagram and system integration, functional description, programming model, and address map and register definitions sections.

1.0

Initial release.

CAN Controller
Document Version

Changes

2013.12.30

Maintenance release

1.0

Maintenance release.

0.1

Preliminary draft.

Introduction to the HPS Component

Document Version

Changes

2015.11.02 Updated Sections:
  • Configuring Peripherals
  • Peripheral Signals Routed to FPGA
2015.05.04 Maintenance release.
2014.12.15 Maintenance release.
2014.02.28
  • Add interfaces to tables
  • Add parameters to General Parameters table

1.2

Maintenance release.

1.1

  • Added debug interfaces
  • Added boot options
  • Corrected slave address width
  • Corrected SDRAM interface widths
  • Added TPIU peripheral
  • Added .sdc file generation
  • Added .tcl script for memory assignments

1.0

Initial release.

0.1

Preliminary draft.

Instantiating the HPS Component

Document Version

Changes

2015.05.04
  • Added note to FGPA-to-HPS SDRAM Interface section
  • Added note to User Clocks section
2014.12.15

User Clock 2 has been removed

2014.06.30

Added address map and register descriptions

2014.02.28

Added sections:

  • Peripheral FPGA Clocks
  • Peripheral Reset Interfaces
  • Boot from FPGA Interface
  • Input-only General Purpose Interfaces

Removed section:

  • General Purpose Interfaces

Updated sections:

  • Trace Port Interface Unit
  • Peripheral Signal Interfaces
  • FPGA-to-HPS Interrupts
2013.12.30

Minor formatting issues

1.1

  • Added debug interfaces.
  • Updated HPS‑to‑FPGA reset interface names.
  • Updated HPS external reset source interface names.
  • Removed DMA peripheral interface clocks.
  • Referred to Address Span Extender.

1.0

Initial release.

0.1

Preliminary draft.

HPS Component Interfaces

Document Version

Changes

2016.05.03 Removed references to FPGA to HPS SDRAM simulation.
2015.11.02 Maintenance release
2015.05.04 Maintenance release
2014.12.15 Maintenance release
2014.11.14
  • Updated the "Simulation Flows" section.
  • Updated the "Generating HPS Simulation Model in Platform Designer (Standard)" section.
2014.02.28

Added new sections:

  • Boot from FPGA Interface
  • General Purpose Input (GPI) Interface

Updated content in sections:

  • Specifying HPS Simulation Model in Platform Designer (Standard)
  • Running HPS RTL Simulation
2013.12.30 Maintenance release

1.1

  • Added debug APB* , STM hardware event, FPGA cross trigger, FPGA trace port interfaces.
  • Added support for post‑fit simulation.
  • Updated some API function names.
  • Removed DMA peripheral clock.

1.0

Initial release.

0.1

Preliminary draft.

Simulating the HPS Component

Document Version

Changes

2021.07.08 Added information about HPS independent power in Booting and Configuration Options.
2020.09.03 Added information about where the HPS IO Configuration is contained in the Typical Preloader Boot Flow section.
2018.07.17
  • Removed I/O State subsection in I/O Configuration section. This content only applies to Intel® Arria® 10 HPS.
  • Added state of dedicated I/O at power up in the I/O Configuration section.
2016.05.27 Changed the name of the internal QSPI reference clock from qspi_clk to qspi_ref_clk; and the external QSPI output clock, from sclk_out to qspi_clk.
2016.05.03
  • Updated SD/MMC device clock values in the CSEL Settings for SD/MMC Controller section.
  • Included read capture delay information in the Quad SPI Flash Delay Configuration section.
  • Added bus mode to the "SD/MMC Controller Default Settings" table in the Default Settings of the SD/MMC Controller section.
  • Changed the name of the internal QSPI reference clock from qspi_clk to qspi_ref_clk; and the external QSPI output clock, from sclk_out to qspi_clk.
2015.11.02 Maintenance Release
2015.05.04
  • Added "Boot Source I/O Mapping" section
  • Removed "*2" multiplier in CSEL3 column of the table in "CSEL Pin Settings for the SD/MMC Controller" section.
  • Corrected frequency values for Device frequency and controller clock in the "NAND Controller CSEL Pin Settings" table in the "CSEL Settings for the NAND Controller" section
  • Removed reference to Mode Reset Command in the "Quad SPI Flash Devices"
  • Clarified "Shared Memory Locations" in "Shared Memory" section
2014.12.15
  • Added the following sections:
    • "Boot Overview"
    • "FPGA Configuration Overview"
    • "Booting and Configuration Options"
    • "Boot Definitions" section with subsections on "Reset", "Boot ROM", "Boot Source I/O Pins", "Flash Memory Devices", "Clock Select", "I/O Configuration", "L4 Watchdog 0 Timer", "Preloader", and "U-Boot Loader".
  • Removed "Shared Memory" section
2014.06.30

Maintenance release

2014.02.28 Correction to "Leading the Preloader" section
2013.12.30
  • Updated figures in the Booting and Configuration Introduction section.
  • Updated the Rest and Boot ROM sections.
  • Updated the Shared Memory Block table.
  • Updated register names in the Full Configuration section.

1.3

  • Expanded shared memory block table.
  • Added CLKSEL tables.
  • Additional minor updates.

1.2

Updated the HPS boot and FPGA configuration sections.

1.1

  • Updated the HPS boot section.
  • Added information about the flash devices used for HPS boot.
  • Added information about the FPGA configuration mode.

1.0

Initial release.

Booting and Configuration