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1. About the RiscFree* IDE
2. Getting Started with the Ashling* RiscFree* IDE for Intel® FPGAs
3. Using Ashling* RiscFree* IDE for Intel® FPGAs with Nios® V Processor System
4. Using Ashling* RiscFree* IDE for Intel® FPGAs with Arm* Hard Processor System
5. Debugging Features with RiscFree* IDE for Intel® FPGAs
6. Debugging with Command-Line Interface
7. Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide Archives
8. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide
A. Appendix
3.1. Importing Nios® V Processor Project
3.2. Building Nios® V Processor Project
3.3. Setting Run Configuration to Download Nios® V Processor Project
3.4. Setting Debug Configuration to Debug Nios® V Processor Project
3.5. Setting Debug Configuration to Debug a Booting Nios® V Processor Project
3.6. Debugging Tools
5.1. Debug Features in RiscFree* IDE
5.2. Processor System Debug
5.3. Heterogeneous Multicore Debug
5.4. Debugging µC/OS-II Application
5.5. Debugging FreeRTOS Application
5.6. Debugging Zephyr Application
5.7. Arm* HPS On-Chip Trace
5.8. Debugging the Arm* Linux Kernel
5.9. Debugging Target Software in an Intel® Simics Simulator Session
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5.7.1. Trace Bar
You can control the trace process using the Trace Bar.
Figure 64. Trace View Bar Options
Trace Bar | Function | Description |
---|---|---|
1 | Fetch Trace | Fetches the trace data from the target trace buffer, decode and populate it in the Trace view. |
2 | Clear Trace | Clears the trace view and the target trace buffer data. |
3 | First Page | Navigates the trace data when there are multiple pages of trace information. |
4 | Previous Page | |
5 | Next Page | |
6 | Last Page | |
7 | Start Capture | Starts the trace capturing. Applicable only when you manually stop the trace using Stop Capture. |
8 | Stop Capture | Stops the trace. |