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Ixiasoft
Visible to Intel only — GUID: ccc1495159661968
Ixiasoft
1. Intel® Arria® 10 Hard Processor System Technical Reference Manual Revision History
Updated for: |
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Intel® Quartus® Prime Design Suite 22.3 |
Document Version |
Changes |
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2022.08.22 | Removed RGMII because it does not support FPGA IO |
2017.05.31 | Removed HMCREGS row from HPS Peripheral Region Map table. Accesses to this address block are not supported. |
2016.10.28 | Renamed MPU Subsystem to Cortex*-A9 MPCore* |
2016.05.27 | Corrected the HPS-FPGA powering scheme. |
2016.05.03 |
Removed low-power double data rate 3 (LPDDR3) as a supported device. |
2015.11.02 | Updated the link to the Memory Maps. |
2015.05.04 | Corrected HPS-FPGA powering scheme. |
2014.12.15 | Maintenance release |
2014.08.18 | Initial release |
Document Version | Changes |
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2017.07.22 |
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2016.10.28 |
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2016.05.27 |
Removed references to PLL counter outputs C9-C15 from the following topics:
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2016.05.03 | Added a section titled "L4 Peripheral Clocks". |
2015.11.02 | Updated Sections:
Added Sections:
Updates:
|
2015.05.04 |
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2014.12.15 | Clock Manager Block Diagram. Updated mux output route. NOC clock added. Peripheral Clocks block update C15 input for PLL1 has been removed throughout document. |
2014.08.18 | Initial release. |
Document Version | Changes |
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2017.07.22 |
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2016.10.28 | Maintenance release. |
2016.05.03 | Maintenance release. |
2015.11.02 | Updated "Reset Pins" section. |
2015.05.04 | "Slave Interface" and "Status Register" sections updated. |
2014.12.15 | Maintenance release. |
2014.08.18 | Initial release. |
Document Version |
Changes |
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2015.11.02 |
|
2015.05.04 | Maintenance release |
2014.12.15 | Maintenance release |
2014.08.18 | Initial release |
Document Version | Changes |
---|---|
2016.10.28 | Maintenance release. |
2016.05.27 | Removed the following references to the Ethernet application interface:
|
2016.05.03 | Maintenance release. |
2015.11.02 | Maintenance release. |
2015.05.04 | Maintenance release. |
2014.12.15 |
|
2014.08.18 | Initial release. |
Date | Version | Changes |
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July 2017 | 2017.07.21 |
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October 2016 | 2016.10.28 | Maintenance release |
May 2016 | 2016.05.27 | Maintenance release |
May 2016 | 2016.05.03 |
|
November 2015 | 2015.11.02 | Clarified initialization steps in "Secure Initialization Overview" section |
May 2015 | 2015.05.04 | Added Address Map and Register information. |
December 2014 | 2014.12.15 |
|
August 2014 | 2014.08.18 | Initial Release |
Document Version |
Changes |
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2021.01.21 | Updated Arria 10 HPS Available Address Maps to explain how to access the registers that are connected to the HPS-to-FPGA AXI* Master Bridge. |
2019.01.01 | Updated ddrConf bitfield description in the ddr_T_main_Scheduler_Ddrconf register to include encodings. |
2018.09.24 | Updated the following section:
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2017.05.31 |
|
2016.10.28 |
|
2016.05.27 | Maintenance release |
2016.05.03 | Maintenance release |
2015.11.02 |
|
2015.05.04 |
|
2014.12.15 |
|
2014.08.18 | Initial release |
Document Version | Changes |
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2023.07.23 | Added maximum frequency values for the fpga2hps_clk, hps2fpga_clk, and lwh2fpga_clk clocks. |
2017.07.22 | Added note about bridge transaction timeout to "HPS-to-FPGA Bridge Clocks and Resets" and "Lightweight HPS-to-FPGA Bridge Clocks and Resets". |
2016.10.28 |
|
2016.05.27 | Maintenance release |
2015.11.02 | Maintenance release |
2015.05.04 | Added address maps and register definitions |
2014.12.15 | Maintenance release |
2014.08.18 |
Initial release. |
Document Version |
Changes |
---|---|
2023.08.28 | Added note regarding Cortex* -A9 output flags. |
2021.05.26 | Added clarification for ACP usage requirements by adding the following chapters:
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2020.08.18 | Added information about maintaining cache coherency in the Accelerator Coherency Port |
2019.06.14 | Added details about arbitration behavior in the SCU when the ACP is not being used in the Implementation Details of the Snoop Control Unit section, |
2016.10.28 |
|
2016.05.27 | Maintenance release |
2016.05.03 | Maintenance release |
2015.11.02 |
|
2015.05.04 |
|
2014.12.15 |
|
2014.08.18 | Initial Release |
Document Version |
Changes |
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2017.07.29 | Added reset requirement for BST |
2016.10.28 | Maintenance release |
2016.05.03 | Maintenance release |
2015.11.02 | Added a description on how the 2 TAP controllers are connected and supporting figures. |
2014.05.04 | Maintenance release. |
2014.12.15 | Maintenance release. |
2014.08.18 |
Initial release. |
Date | Version | Changes |
---|---|---|
October 2016 | 2016.10.28 | Maintenance Release |
May 2016 | 2016.05.27 | Maintenance Release |
May 2016 | 2016.05.03 | Maintenance Release |
November 2015 | 2015.11.02 |
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May 2015 | 2015.05.04 |
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December 2014 | 2014.12.15 | Added the "RAM and ECC Memory Organization Example" subsection to the "ECC Structure" section Added the following subsections in the "Indirect Memory Access" section:
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August 2014 | 2014.08.18 | Initial Release |
Document Version |
Changes |
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2014.08.18 | Initial release |
Document Version |
Changes |
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2023.08.28 | Added a note in the Timing Registers section. The note describes the NAND flash controller behavior in Boot mode and Performance mode. |
2016.05.27 | Added a link to the Supported Flash Devices for Arria 10 SoC webpage. |
2016.05.03 |
Added information about determining how many CE/RB signals are available based on the selected pins. |
2015.11.02 |
|
2015.05.04 | Added information about clearing out the ECC before the feature is enabled |
2014.12.15 | Maintenance release |
2014.08.18 |
Initial release |
Document Version | Changes |
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2023.06.29 | Clarified the SD/MMC Controller signals that are routed to FPGA I/O |
2021.07.08 | Changed the SD Card Clock Frequency in Changing the Card Clock Frequency. |
2017.07.22 | Corrected the MMC Support Matrix table in the "MMC Support Matrix" section. |
2016.10.28 | Removed SPI support in tables in the Features section. |
2016.05.27 | Added a link to the Supported Flash Devices for Arria 10 SoC webpage. |
2016.05.03 | Maintenance release |
2015.11.02 |
|
2015.05.04 | Added information about clearing out the ECC before the feature is enabled |
2014.12.15 | Maintenance release |
2014.08.18 | Initial release |
Document Version | Changes |
---|---|
2020.08.18 | Added clarification to the description of the QSPI register, indaddrtrig |
2019.07.09 | Added a new section, Write Request, with WREN and RDSR information |
2019.06.14 | Maintenance release |
2016.10.28 | Maintenance release |
2016.05.27 |
|
2016.05.03 | Maintenance release |
2015.11.02 |
|
2015.05.04 | Added information about clearing out the ECC before the feature is enabled |
2014.12.15 | Maintenance release |
2014.08.18 | Initial release |
Document Version | Changes |
---|---|
2017.07.22 | Added information about DMA requiring that caches need to be enabled |
2016.10.28 | Maintenance release |
2016.05.27 | Maintenance release |
2016.05.03 | Maintenance release |
2015.11.02 |
|
2015.05.04 |
|
2014.12.15 | Maintenance release |
2014.08.18 | Initial release |
Document Version | Changes |
---|---|
2023.01.20 | Added link to the A10 SGMII Reference Design. |
2022.08.22 | Removed RGMII because it does not support FPGA IO |
2021.04.09 | Added emac_clk_tx_i handling requirement for exported HPS EMAC GMII interface in the EMAC FPGA Interface Initialization section. |
2020.08.18 | Updated EMAC HPS Interface Initialization to clarify how to verify RX PHY clocks after bringing the Ethernet PHY out of reset. |
2019.06.14 |
|
2016.10.28 |
|
2016.05.27 | Removed references to the Application Interface (also known as the switch interface). This feature is not supported in this device. |
2016.05.03 | Maintenance release. |
2015.11.02 |
|
2015.05.04 |
|
2014.12.06 |
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2014.08.18 | Initial release. |
Document Version |
Changes |
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2018.01.26 | Added steps for enabling ECC. |
2016.10.28 | Maintenance release. |
2016.05.03 | Maintenance release. |
2015.11.02 |
|
2015.05.04 | Maintenance release. |
2014.12.15 |
|
2014.08.18 |
Initial release. |
Document Version | Changes |
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2015.11.02 |
|
2015.05.04 | Maintenance release. |
2014.12.15 |
|
2014.08.18 | Initial release. |
Document Version | Changes |
---|---|
2015.11.02 |
|
2015.05.04 |
|
2014.12.15 |
|
2014.08.18 | Initial release. |
Document Version | Changes |
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2015.11.02 | Renamed Interface Pins section to HPS I/O Pins and moved this section and FPGA Routing under UART Controller Signal Description |
2015.05.04 | Maintenance release. |
2014.12.15 |
|
2014.08.18 | Initial release. |
Document Version | Changes |
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2014.12.15 |
|
2014.08.18 | Initial release. |
Version | Changes |
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2014.08.18 | Initial release. |
Document Version | Changes |
---|---|
2015.11.02 | Added note to "Watchdog Timer Counter" section. |
2015.05.04 | Maintenance release. |
2014.12.15 |
|
2014.08.18 | Initial release |
Document Version |
Changes |
---|---|
2019.06.14 | Updated the PU_DRV_STRG and PD_DRV_STRG fields in the pinmux_dedicated_io_1 through pinmux_dedicated_io_17 registers in the io48_pin_mux_dedicated_io_grp. |
2018.09.24 | Updated the following section:
|
2016.10.28 | Maintenance release |
2016.05.27 | Maintenance release. |
2016.05.03 | Maintenance release |
2015.11.02 | Maintenance release |
2015.05.04 | Added address maps and register definitions |
2014.08.18 | Initial release |
Document Version |
Changes |
---|---|
2016.05.03 | Removed FPGA‑to‑HPS SDRAM interface |
2015.11.02 | Maintenance release |
2015.05.04 | Maintenance release |
2014.12.15 | Maintenance release |
2014.08.18 | Initial release |
Document Version |
Changes |
---|---|
2023.07.23 | Added maximum frequency values for the f2sdram0_clock, f2sdram1_clock, and f2sdram2_clock. |
2023.01.10 | Corrected the Enable UART Interrupts interface name, from s2f_usb1_interrupt to h2f_usb1_interrupt. |
2016.05.27 | Removed FPGA EMAC Switch Interface section. The application interface (also called the switch interface) is not supported. |
2016.05.03 | Maintenance release. |
2015.11.02 | Added content regarding peripheral pin placement in HPS shared and dedicated I/O to the "Configuring Peripherals" section. |
2015.05.04 |
|
2014.12.15 |
Initial release. |
Document Version | Changes |
---|---|
2016.05.27 | Removed FPGA EMAC Switch Interface section. The application interface (also called the switch interface) is not supported. |
2016.05.03 | Maintenance release. |
2015.11.02 |
|
2015.05.04 | Maintenance release. |
2014.12.15 | Initial release. |
Document Version |
Changes |
---|---|
2016.05.27 | Removed FPGA EMAC Switch Interface section. The application interface (also called the switch interface) is not supported. |
2016.05.03 | Removed references to FPGA to HPS SDRAM simulation. |
2015.11.02 | Added information about the signals on the "Advanced FPGA Placement" tab. |
2015.05.04 | Maintenance release. |
2014.12.15 |
Maintenance release. |
2014.08.15 |
Initial release. |
Document Version | Changes |
---|---|
2018.11.02 | Added note regarding SD card image partitioning in the SD/MMC Flash Devices section. |
2017.12.15 | Removed CM_PLL_CLK* signals from "Boot Source MUX Selects" table in Boot Source I/O Pins section |
2017.07.22 |
|
2017.07.10 |
|
2017.05.31 |
|
2016.10.28 | Modified the "Remapping the On-Chip RAM" diagram in the "Typical Boot Flow (Non-secure)" section |
2016.05.27 |
|
2016.05.03 |
|
2015.12.11 | Updated the Full FPGA Reconfiguration section with the supported reconfiguration options. |
2015.11.02 | Added Intel® Quartus® Prime setting information to "Early I/O Release FPGA Configuration Through HPS" section |
2015.06.12 |
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2015.05.04 |
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2014.12.15 |
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2014.08.18 | Initial release |