F-Tile JESD204B Intel® FPGA IP Design Example User Guide

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ID 729497
Date 7/15/2022
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile JESD204B Intel® Agilex™ FPGA IP Design Example User Guide 2. F-Tile JESD204B Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the F-Tile JESD204B Design Example 4. Document Revision History for the F-Tile JESD204B Intel® FPGA IP Design Example User Guide
2. F-Tile JESD204B Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Software Requirements 2.3. Generating the Design 2.4. Simulating the Design Example Testbench 2.5. Compiling the Design Example 2.6. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
2.4. Simulating the Design Example Testbench x
2.4.1. Simulation Testbench
3. Detailed Description for the F-Tile JESD204B Design Example x
3.1. Supported Configurations 3.2. System Components 3.3. Design Example Clock and Reset 3.4. Design Example Signals 3.5. F-Tile JESD204B Design Example Status and Control Registers 3.6. Hardware Test for System Console Control Design Example
3.2. System Components x
3.2.1. JESD204B Subsystem in Platform Designer 3.2.2. Parallel I/O Core 3.2.3. Core PLL 3.2.4. SPI Master 3.2.5. Transport Layer 3.2.6. Test Pattern Generator 3.2.7. Test Pattern Checker
3.6. Hardware Test for System Console Control Design Example x
3.6.1. Board Connectivity
1. About the F-Tile JESD204B Intel® Agilex™ FPGA IP Design Example User Guide
2. F-Tile JESD204B Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the F-Tile JESD204B Design Example
4. Document Revision History for the F-Tile JESD204B Intel® FPGA IP Design Example User Guide

2.6. Compiling and Testing the Design

The JESD204B Intel® FPGA IP parameter editor allows you to run the design example on a target development kit.

Perform the following steps to compile the design and program the development board:

  1. Launch the Intel® Quartus® Prime software and compile the design (Processing > Start Compilation).
    The timing constraints and pin assignments for the design example and the design components are automatically loaded during design example compilation.
  2. Connect the development board to the host computer either by connecting a USB cable to the on-board Intel® FPGA Download Cable II component or using an external Intel® FPGA Download Cable II module to connect to the external JTAG connector.
  3. Launch the Clock Control application that is included with the development board, and set the clock settings according to the selected data rate.
    Table 8.  Clock Settings
    Clock Name Clock Frequency
    refclk_xcvr Select the frequency for the transceiver PLL reference clock in the IP parameter editor.
    refclk_core Select the frequency for the core PLL reference clock in the IP parameter editor.
    mgmt_clk 100 MHz
    Figure 6. Clock Control GUI SettingThis example shows the clock control GUI setting for a design example running at 6.144 Gbps on an F-tile device using the Intel® Agilex™ I-Series Transceiver-SoC Development Kit.
    Note: For Si539-A, set OUT9A with the same values as OUT9 to avoid clock frequency calculation issues. Refer to the Intel® Agilex™ I-Series FPGA and SoC FPGA website for more information.
  4. If you are performing external loopback test for designs targeting Intel® Agilex™ I-Series Transceiver-SoC Development Kit (F-Tile), attach the FMC+ loopback module at the FMC+ connector A (J7D).
  5. Configure the FPGA on the development board with the generated programming file (.sof file) using the Intel® Quartus® Prime Programmer.
To run the hardware testing using the Tcl script, refer to the Hardware Test for System Console Control Design Example section.
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