F-Tile JESD204B Intel® FPGA IP Design Example User Guide

ID 729497
Date 7/15/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.6.1. Board Connectivity

If you are performing hardware testing on the selected Intel development kits, generate the design example with the appropriate target development kit selected.
Note: Running the hardware test with the design generated as-is is only possible when the F-Tile JESD204B Intel® FPGA IP is configured in duplex data path mode (i.e. with both TX and RX data paths present). Make your own modifications to the design to run the hardware test if generating a simplex data path design.
Table 21.   Intel® Agilex™ I-Series Transceiver-SoC Development Kit Board ConnectivityThe generated design has pre-assigned pins that target the relevant boards. The table describes the board connectivity of key design ports for all supported target development kits.
Port Name Port Description Board Component Component Description
global_rst_n Global reset U3C Refer to the Intel® MAX® 10 FPGA Device Datasheet
refclk_xcvr Transceiver reference clock input U18 Si5391 Clock Generator-i (OUT9)
refclk_core Core PLL reference clock input U18 Si5391 Clock Generator-i (OUT6)
mgmt_clk Control clock U18 Si5391 Clock Generator-i (OUT0)
tx_serial_data TX serial data J7D FMC+ Connector A (F-Tile Bank 12C)
rx_serial_data RX serial data J7D FMC+ Connector A (F-Tile Bank 12C)