F-Tile JESD204B Intel® FPGA IP Design Example User Guide

ID 729497
Date 7/15/2022
Public

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Document Table of Contents

2.3.1. Design Example Parameters

The F-Tile JESD204B Intel® FPGA IP parameter editor includes an Example Design tab for you to specify certain parameters before generating the design example.
Table 5.  Parameters in the Example Design Tab
Parameter Options Description
Available Example Designs None (Default) No design examples selected.
System Console Control Design example with System Console control.
Example Design Files Simulation Generate simulation fileset.
Synthesis Generate synthesis fileset.
Generated HDL Format for Simulation Verilog (Default) Verilog HDL format for entire simulation fileset.
VHDL VHDL format for generated top-level wrapper file set.
Generated HDL Format for Synthesis Verilog (Default) Verilog HDL format for synthesis fileset.
Example Design Customizations Generate 3-wire SPI module Turn on to enable 3-wire SPI interface instead of 4-wire SPI interface.
Target Development Kit None (Default)

This option excludes hardware aspects for the design example. All the pin assignments are set to virtual pins.

Intel® Agilex™ I-series Transceiver-SoC Development Kit This option automatically selects the project's target device to match the device on the development kit. All pin assignments are set according to the development kit.