F-Tile JESD204B Intel® FPGA IP Design Example User Guide

ID 729497
Date 7/15/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.1. Design Example Block Diagram

Figure 2.  F-Tile JESD204B Design Example High-level Block Diagram

The design example consists of the following modules:

  • Platform Designer system
    • JESD204B subsystem
      • F-Tile JESD204B Intel® FPGA IP
      • F-Tile Reference and System PLL Clocks IP
      • Reset sequencers
      • Avalon® memory-mapped bridge
    • JTAG to Avalon master bridge—for System Console control design example only
    • Parallel I/O (PIO) controller
    • Core PLL
    • Serial Port Interface (SPI)—master module
  • Test pattern generator (for duplex and simplex TX data path only)
  • Test pattern checker (for duplex and simplex RX data path only)
  • Assembler—TX transport layer (for duplex and simplex TX data path only)
  • Deassembler—RX transport layer (for duplex and simplex RX data path only)