F-Tile JESD204B Intel® FPGA IP Design Example User Guide

ID 729497
Date 7/15/2022
Public

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Document Table of Contents

3.1. Supported Configurations

The design examples only support a limited set of F-Tile JESD204B IP parameter configurations. The IP parameter editor allows you to generate a design example only if the parameter configurations matches those in the following tables.
Note: If you cannot generate a design example that fully matches your desired parameter settings, choose the closest allowable parameter values for the generation. Modify the post-generated design parameters manually in the Intel® Quartus® Prime software to match your desire parameter settings. Refer to the F-Tile JESD204B Intel® FPGA IP User Guide for more details on the rules and ranges that govern each IP and transport layer parameter.
Table 9.  Supported F-Tile JESD204B IP Parameter Configurations (L, M, F Values)
L M F
1 1 2
1 1 3
1 1 4
1 1 8
1 2 3
1 2 4
1 2 8
1 4 8
2 1 1
2 1 2
2 1 3
2 1 4
2 1 8
2 2 2
2 2 3
2 2 4
2 2 8
2 4 3
2 4 4
2 4 8
2 8 8
4 1 1
4 1 2
4 1 3
4 1 4
4 16 8
4 2 1
4 2 2
4 2 3
4 2 4
4 2 8
4 4 2
4 4 3
4 4 4
4 4 8
4 8 3
4 8 4
4 8 8
6 1 1
6 3 1
8 1 1
8 1 2
8 16 3
8 16 4
8 16 8
8 2 1
8 2 2
8 2 3
8 2 4
8 2 8
8 32 8
8 4 1
8 4 2
8 4 3
8 4 4
8 4 8
8 8 2
8 8 3
8 8 4
8 8 8
Table 10.  Supported F-Tile JESD204B IP Parameter ConfigurationsTable lists the parameters for the F-Tile JESD204B IP. The F-Tile JESD204B IP parameters are governed by various rules and ranges that are described in the F-Tile JESD204B Intel® FPGA IP User Guide. Refer to the F-Tile JESD204B Intel® FPGA IP User Guide for more details on the legal parameter values. The value ranges given below should be considered as a subset of the allowable values described in the F-Tile JESD204B Intel® FPGA IP User Guide.
F-Tile JESD204B IP Parameters Values
Wrapper Options Both Base and PHY
Data Path
  • Receiver
  • Transmitter
  • Duplex
JESD204B Subclass 1
Data Rate

Any valid value1

PCS Option Enabled Soft PCS
Bonding Mode
  • Bonded
  • Non-bonded
PLL/CDR Reference Clock Frequency Any valid value
System PLL Frequency Data rate/20
Enable Bit Reversal and Byte Reversal Any valid value
Enable Transceiver Dynamic Reconfiguration

Any valid value

L
  • 1
  • 2
  • 4
  • 62
  • 8
M
  • 1
  • 2
  • 33
  • 4
  • 8
  • 16
  • 32
Enable manual F configuration
  • No
  • Yes only for the following configuration:

    L=8, M=8, F=8, S=5, N’=12, N=12

F
  • Auto calculated
  • Manual F configuration only allowed for the following configuration:

    L=8, M=8, F=8, S=5, N’=12, N=12

N Integer, range 12 – 16
N’
  • 16
  • 12 only for the following configurations:
    • L=8, M=8, F=8, S=5, N=12
    • F=3, N’=12, N=12
S Any valid value
K Any valid value
Enable Scramble (SCR) Any valid value
CS Integer, range 0 – 3
CF 0
High Density User Data Format (HD)
  • 0
  • 1 only for F=1
Enable Error Code Correction (ECC_EN) Any valid value
1 Refer to F-Tile JESD204B Intel® FPGA IP User Guide for more details on maximum and minimum data rates for your target device.
2 L=6 is only allowed when F=1.
3 M=3 is only allowed for L=6.