F-Tile JESD204B Intel® FPGA IP Design Example User Guide

ID 729497
Date 7/15/2022
Public

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3.2.5. Transport Layer

The transport layer in the design example consists of an assembler at the TX path and a deassembler at the RX path. The transport layer for both the TX and RX path is instantiated in the top level RTL file, not in the Platform Designer project.

Note: When the simplex TX data path option is selected, only the assembler is instantiated in the design example. When the simplex RX data path option is selected, only the deassembler is instantiated in the design example. When the duplex data path option is selected, both assembler and deassembler is instantiated in the design example.

The transport layer provides the following services to the application layer (AL) and the data link layer (DLL):

  • Assembler at the TX path:
    • Maps the conversion samples from the AL (through the Avalon® streaming interface) to a specific format of non-scrambled octets, before streaming them to the DLL.
    • Reports AL error to the DLL if it encounters a specific error condition on the Avalon® streaming interface during TX data streaming.
  • Deassembler at the RX path:
    • Maps the descrambled octets from the DLL to a specific conversion sample format before streaming them to the AL (through the Avalon® streaming interface).
    • Reports AL error to the DLL if it encounters a specific error condition on the Avalon® streaming interface during RX data streaming.

The transport layer has many customization options and you can modify the transport layer RTL to customize it to your specifications. Furthermore, for certain parameters like L, F, and N, the transport layer shares the CSR values with the JESD204B IP core.