F-Tile JESD204B Intel® FPGA IP Design Example User Guide

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ID 729497
Date 12/02/2024
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile JESD204B Intel Agilex® 7 FPGA IP Design Example User Guide 2. F-Tile JESD204B Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the F-Tile JESD204B Design Example 4. Document Revision History for the F-Tile JESD204B Intel® FPGA IP Design Example User Guide
2. F-Tile JESD204B Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Simulating the Design Example Testbench 2.5. Compiling the Design Example 2.6. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
2.4. Simulating the Design Example Testbench x
2.4.1. Simulation Testbench
3. Detailed Description for the F-Tile JESD204B Design Example x
3.1. Supported Configurations 3.2. System Components 3.3. Design Example Clock and Reset 3.4. Design Example Signals 3.5. F-Tile JESD204B Design Example Status and Control Registers 3.6. Hardware Test for System Console Control Design Example
3.2. System Components x
3.2.1. JESD204B Subsystem in Platform Designer 3.2.2. Parallel I/O Core 3.2.3. Core PLL 3.2.4. SPI Master 3.2.5. Transport Layer 3.2.6. Test Pattern Generator 3.2.7. Test Pattern Checker
3.6. Hardware Test for System Console Control Design Example x
3.6.1. Board Connectivity
1. About the F-Tile JESD204B Intel Agilex® 7 FPGA IP Design Example User Guide
2. F-Tile JESD204B Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the F-Tile JESD204B Design Example
4. Document Revision History for the F-Tile JESD204B Intel® FPGA IP Design Example User Guide

3.6. Hardware Test for System Console Control Design Example

Perform the following instructions to run the hardware test for the design example using the system console control in the Quartus® Prime software.
Note: This hardware test assumes that you configured your design in duplex mode for system console control. Make your own modifications if you are using simplex mode design.
  1. Launch the System Console tool from Quartus® Prime (Tools > System Debugging Tools > System Console).
  2. In the TCL Console command prompt, type get_service_paths master to print a list of devices connected to your JTAG chain.
  3. Open the main.tcl script located in the ed_synth/system_console/ directory in any text editor of your choice and locate the following line. 
    set master_index [expr {$master_list_length - 2}]
  4. Adjust the master_index offset as necessary to reflect your JTAG chain configuration such that the master_index always points to the Intel Agilex® 7 device and save the file.
    Figure 9. Example of master_index Configurations to Reflect JTAG Chain
  5. In the TCL Console command prompt, navigate to the ed_synth/system_console/ directory and execute the main.tcl script (source main.tcl). Your TCL Console window should resemble the following figure.
    Figure 10. Source main.tcl
  6. Type start_basic_test at the command prompt to execute the link setup and test procedure.

    This procedure executes a set of instructions to set up the pattern generator and checker to transmit and check ramp pattern, configure the JESD204B IP PHY internal serial loopback mode and report link status.

    The following figure illustrates the expected result from a successful link setup and test.
    Figure 11. Successful Test in the System Console
  7. Should the test fail due to a lane deskew error, use the rbd_offset procedure described in the following table to offset the default RBD error.

    Refer to the F-Tile JESD204B Intel® FPGA IP User Guide for more details on using the RBD offset.

    Table 20.  Procedures in the main.tcl System Console Script The table describes useful procedures in the main.tcl that may be helpful in debugging.
    Procedure Values Description
    get_service_paths {master} Reports all devices that are connected to the JTAG chain. Use this information to set the master index to point to the Intel Agilex® 7 device.
    get_master_index N/A Sets the targeted device master index. Use get_service_paths master to determine the offset of the Intel Agilex® 7 device in the JTAG chain, and edit the offset in this procedure accordingly.
    start_basic_test N/A Main procedure that sets up link serial loopback mode, pattern generator and checker test mode, pulses sysref, and reports link status.
    reset N/A Global reset
    force_tx_link_frame_reset {0,1}

    0: Deasserts TX link and frame resets

    1: Asserts and holds TX link and frame resets

    Note: TX link and frame clock domains should be held in reset while writing to F-Tile JESD204B IP TX CSR.
    force_rx_link_frame_reset {0,1}

    0: Deasserts RX link and frame resets

    1: Asserts and holds RX link and frame resets

    Note: RX link and frame clock domains should be held in reset while writing to F-Tile JESD204B IP RX CSR.
    sloopback {0,1}

    0: Disables internal serial loopback

    1: Enables internal serial loopback
    set_testmode {alt, ramp, prbs}

    alt: Sets pattern generator and checker to alternate pattern

    ramp: Sets pattern generator and checker to ramp pattern

    prbs: Sets pattern generator and checker to PRBS pattern
    rbd_offset {integer} Adjusts RBD offset value to eliminate RX lane deskew error.
    sysref N/A Single pulse sysref.
    read_status_pio N/A Reads status PIO registers. PIO status configuration:
    • Bit 0 – Core PLL locked
    • Bit 1 – TX reset handshake acknowledge status
    • Bit 2 – RX reset handshake acknowledge status
    • Bit 3 – Test pattern checker data error (for duplex and simplex RX data path only)
    • Bit 4 – TX link error (use read_err_status procedure to report error description
    • Bit 5 – RX link error (use read_err_status procedure to report error description
    read_error_status N/A Reads JESD204B IP error status registers. Refer to the F-Tile JESD204B IP register maps for detailed description of status registers.
    clear_error_status N/A Clears JESD204B IP error status registers
    read_rx_status() N/A Reads JESD204B IP rx_status0 register. Refer to the F-Tile JESD204B IP register maps for detailed description of status registers.
    read_tx_status() N/A Reads JESD204B IP tx_status0 register. Refer to the F-Tile JESD204B IP register maps for detailed description of status registers.
    read_rx_syncn_sysref_ctrl N/A Reads JESD204B IP syncn_sysref_ctrl register. Refer to the F-Tile JESD204B IP register maps for detailed description of status registers.
    wait_seconds {integer} Waits for {integer} seconds.
    wait_minutes {integer} Waits for {integer} minutes.
    eval_test N/A Reports link status.

Section Content
Board Connectivity

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