F-Tile JESD204B Intel® FPGA IP Design Example User Guide

ID 729497
Date 7/15/2022
Public

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Document Table of Contents

2.3.2. Directory Structure

The F-Tile JESD204B design example directories contain the generated files for the design examples.
Figure 3. Directory Structure for F-Tile JESD204B Design Example
Table 6.  Directory Files
Directory/File Description
ed_sim The folder that contains simulation testbench files.
ed_sim/models The folder that contains the testbench and source files.
ed_sim/models/pattern The folder that contains the source files for the pattern generator/checker.
ed_sim/models/transport_layer The folder that contains the source files for the transport layer.
ed_sim/setup_scripts The folder that contains the test flow setup scripts.
ed_sim/xcelium The folder that contains the test flow run scripts for Xcelium* Parallel simulator. Also serves as the working directory for the simulator.
ed_sim/mentor The folder that contains the test flow run scripts for ModelSim* or QuestaSim* simulator. Also serves as the working directory for the simulator.
ed_sim/synopsys/vcs The folder that contains the test flow run scripts for VCS* simulator. Also serves as the working directory for the simulator.
ed_sim/synopsys/vcsmx The folder that contains the test flow run scripts for VCS* MX simulator. Also serves as the working directory for the simulator.
ed_synth The folder that contains design example synthesizable components.
ed_synth/intel_s10_user_rst_clkgate_0 The folder that contains the Platform Designer-generated modules of the Reset Release IP.
ed_synth/intel_jesd204_se_outbuf_1bit The folder that contains the Platform Designer-generated modules of the bidirectional I/O buffer for the 3-wire SPI interface.
ed_synth/ip The folder that contains Platform Designer-instantiated IP modules.
ed_synth/jesd_f_ed_qsys_<data path> The folder that contains Platform Designer-generated modules from the jesd_f_ed_qsys_<data path>.qsys system.
ed_synth/jesd_f_ss_<data path> The folder that contains Platform Designer-generated modules from the jesd_f_ss_<data path>.qsys system.
ed_synth/pattern The folder that contains the source files for the pattern generator/checker.
ed_synth/transport_layer The folder that contains the source files for the transport layer.

ed_synth/intel_jesd204b_f_ed_<data path>.qpf

ed_synth/intel_jesd204b_f_ed_<data path>.qsf

Intel® Quartus® Prime project and settings files
ed_synth/jesd_f_ed_qsys_<data path>.qsys Platform Designer top level system
ed_synth/jesd_f_ss_<data path>.qsys Platform Designer subsystem
ed_synth/intel_jesd204b_f_ed_<data path>.sv Top level HDL source file
ed_synth/intel_jesd204b_f_ed_<data path>.sdc Top level design constraints file