F-Tile JESD204B Intel® FPGA IP Design Example User Guide

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ID 729497
Date 7/15/2022
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile JESD204B Intel® Agilex™ FPGA IP Design Example User Guide 2. F-Tile JESD204B Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the F-Tile JESD204B Design Example 4. Document Revision History for the F-Tile JESD204B Intel® FPGA IP Design Example User Guide
2. F-Tile JESD204B Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Software Requirements 2.3. Generating the Design 2.4. Simulating the Design Example Testbench 2.5. Compiling the Design Example 2.6. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
2.4. Simulating the Design Example Testbench x
2.4.1. Simulation Testbench
3. Detailed Description for the F-Tile JESD204B Design Example x
3.1. Supported Configurations 3.2. System Components 3.3. Design Example Clock and Reset 3.4. Design Example Signals 3.5. F-Tile JESD204B Design Example Status and Control Registers 3.6. Hardware Test for System Console Control Design Example
3.2. System Components x
3.2.1. JESD204B Subsystem in Platform Designer 3.2.2. Parallel I/O Core 3.2.3. Core PLL 3.2.4. SPI Master 3.2.5. Transport Layer 3.2.6. Test Pattern Generator 3.2.7. Test Pattern Checker
3.6. Hardware Test for System Console Control Design Example x
3.6.1. Board Connectivity
1. About the F-Tile JESD204B Intel® Agilex™ FPGA IP Design Example User Guide
2. F-Tile JESD204B Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the F-Tile JESD204B Design Example
4. Document Revision History for the F-Tile JESD204B Intel® FPGA IP Design Example User Guide

2.4.1. Simulation Testbench

The simulation design-under-test (DUT) is the generated design example which includes a synthesizable pattern generator and checker. The figures below show the testbench block diagram for the simplex and duplex options.

Figure 4. Simulation Testbench Block Diagram (Simplex TX or RX)
Note: Both simplex TX and simplex RX design examples generate the same testbench. The testbench is identical to duplex design, except duplex JESD204B IP is replaced with TX/RX simplex IPs. The testbench instantiates two JESD204B IPs: one simplex TX IP, one simplex RX IP. The TX serial data output of the simplex TX is connected to the RX serial data input of the simplex RX. Pattern generator and pattern checker are generated in simplex simulation testbench to demonstrate the IP in loopback.
Figure 5. Simulation Testbench Block Diagram (Duplex)

The simulation flow replaces the JTAG to Avalon® master bridge module in the Platform Designer system of the System Console control design example with the Avalon® memory-mapped master bus functional model (BFM). This BFM enables a testbench to send Avalon® memory-mapped read/write commands to the design example registers to mimic the functionality of System Console.

The testbench provided in the simulation flow (/models/tb_top.sv) executes the following steps:

  1. Resets the DUT.
  2. Initializes the BFM.
  3. Executes the Avalon® memory-mapped commands to initialize the DUT in the following mode:
    • Pattern generator/checker set to PRBS pattern
  4. Waits for the DUT to initialize the user mode.
  5. Reports the F-Tile JESD204B link status.

When the simulation ends, the following messages are shown at end.

Table 7.  Simulation Messages and Description
Message Description
Pattern Checker(s): Data error(s) found! Pattern mismatch errors found on the pattern checker
Pattern Checker(s): OK! No errors found on the pattern checker
Pattern Checker(s): No valid data found! No valid data received by pattern checker
JESD204B Tx Core(s): Tx link error(s) found! Link errors reported by JESD204B IP TX
JESD204B Tx Core(s): OK! No link errors reported by JESD204B IP TX
JESD204B Rx Core(s): Rx link error(s) found! Link errors reported by JESD204B IP RX
JESD204B Rx Core(s): OK! No link errors reported by JESD204B IP RX
TESTBENCH_PASSED: SIM PASSED! Overall simulation passed
TESTBENCH_FAILED: SIM FAILED! Overall simulation failed
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