F-Tile JESD204B Intel® FPGA IP Design Example User Guide

ID 729497
Date 7/15/2022
Public

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3.2.3. Core PLL

The core PLL module generates the clocks for the FPGA core fabric. An IOPLL module is instantiated as the core PLL.

The core PLL uses an external clock input as its reference clock to generate two derivative clocks from a single VCO:

  • Link clock
  • Frame clock
Table 15.  Core PLL Outputs
Clock Formula Description
Link Clock Serial data rate/40 The link clock clocks the JESD204B IP core link layer and the link interface of the transport layer.
Frame Clock Derived based on settings; refer to fTXframe and fRXframe for Different F Parameter Settings. The frame clock clocks the transport layer, test pattern generators and checkers, and any downstream modules in the FPGA core fabric.

For the frame clock, when the F parameter is 1, 2, or 3, the resulting frame clock frequency easily exceeds the capability of the core PLL to generate and close timing. The top level RTL file, (intel_jesd204b_f_ed_<data path>.sv), defines the frame clock division factor parameters, F1_FRAMECLK_DIV (for cases with F = 1) and F2_FRAMECLK_DIV (for cases with F = 2). F = 3 uses a constant division factor of 2. This factor enables the transport layer and test pattern generator to operate at a divided factor of the required frame clock rate by widening the data width accordingly.

Note: For F-Tile JESD204B IP design examples, F1_FRAMECLK_DIV is set to 4 and F2_FRAMECLK_DIV is set to 2.

These examples show how to derive the frame clock frequency:

Example 1: The actual frame clock for a serial data rate of 10 Gbps and F = 1 is:

(10000/(10 × 1)) / F1_FRAMECLK_DIV = 1000 / 4 = 250 MHz

Example 2: The actual frame clock for a serial data rate of 6 Gbps and F = 3 is:

(6000/(10 × 3)) / 2 = 200 / 2 = 100 MHz

Frame Clock and Link Clock Relationship

The frame clock and link clock are synchronous. For the derived F mode, the ratio of link_clk period to frame_clk period is given by this formula:

link_clk period to frame_clk period ratio = 32xL/(MxSxN')
Table 16.  fTXframe and fRXframe for Different F Parameter Settings
  • fTXlink is the TX link clock frequency
  • fRXlink is the RX link clock frequency
F Parameter fTXframe(txframe_clk frequency) fRXframe(rxframe_clk frequency)
1 fTXlinkx(4/F1_FRAMECLK_DIV) fRXlinkx(4/F1_FRAMECLK_DIV)
2 fTXlinkx(2/F2_FRAMECLK_DIV) fRXlinkx(2/F2_FRAMECLK_DIV)
3 fTXlinkx(2/3) fRXlinkx(2/3)
4 fTXlink fRXlink
8 fTXlink/2 fRXlink/2
Note: The IOPLL is generated with the Use Nondedicated Feedback Path option being disabled (default setting). You can turn on the Use Nondedicated Feedback Path option in the IP parameter editor to utilize the clock resources efficiently after the design example is successfully generated. Refer to the Clock Feedback Modes section of Intel® Agilex™ Clocking and PLL User Guide for more information about this option.