Visible to Intel only — GUID: wpa1646322013697
Ixiasoft
Visible to Intel only — GUID: wpa1646322013697
Ixiasoft
2.16.3. TX 2-Step Timestamp Interface
A separate TX 2-step timestamp interface is available for each supported port within a reconfiguration group.
{msb, lsb} == {<i/o>_p2_ptp_<signals>, <i/o>_p0_ptp_<signals>}
Maximum Number of Ports | Applicable Reconfiguration Groups | Signal Name |
---|---|---|
1 | FGT: 25GE-1 Reconfigurable 50GE-1 Reconfigurable FHT: 50GE-1 Reconfigurable 100GE-1 Reconfigurable |
Port 0: i_p0_ptp_ts_reg i_p0_ptp_fp[<w>-1:0] o_p0_ptp_ets_valid o_p0_ptp_ets[95:0] o_p0_ptp_ets_fp[<w>-1:0] where <w> is the timestamp fingerprint width |
2 | FGT: 100GE-2 Reconfigurable FHT: 100GE-2 Reconfigurable 200GE-2 Reconfigurable |
Port 0: i_p0_ptp_ts_reg i_p0_ptp_fp[<w>-1:0] o_p0_ptp_ets_valid o_p0_ptp_ets[95:0] o_p0_ptp_ets_fp[<w>-1:0] Port 1: i_p1_ptp_ts_reg i_p1_ptp_fp[<w>-1:0] o_p1_ptp_ets_valid o_p1_ptp_ets[95:0] o_p1_ptp_ets_fp[<w>-1:0] where <w> is the timestamp fingerprint width |
4 | FGT: 100GE-4 Reconfigurable 400GE-8 Reconfigurable 200GE-4 Reconfigurable FHT: 100GE-4 Reconfigurable 400GE-4 Reconfigurable 200GE-4 Reconfigurable |
Port 0: i_p0_ptp_ts_reg i_p0_ptp_fp[<w>-1:0] o_p0_ptp_ets_valid o_p0_ptp_ets[95:0] o_p0_ptp_ets_fp[<w>-1:0] Port 1: i_p1_ptp_ts_reg i_p1_ptp_fp[<w>-1:0] o_p1_ptp_ets_valid o_p1_ptp_ets[95:0] o_p1_ptp_ets_fp[<w>-1:0] Port 2: i_p2_ptp_ts_reg i_p2_ptp_fp[<w>-1:0] o_p2_ptp_ets_valid o_p2_ptp_ets[95:0] o_p2_ptp_ets_fp[<w>-1:0] Port 3: i_p3_ptp_ts_reg i_p3_ptp_fp[<w>-1:0] o_p3_ptp_ets_valid o_p3_ptp_ets[95:0] o_p3_ptp_ets_fp[<w>-1:0] where <w> is the timestamp fingerprint width |