F-Tile Ethernet Multirate Intel® FPGA IP User Guide

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ID 714307
Date 5/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. F-Tile Ethernet Multirate Intel FPGA IP User Guide Archives 8. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide
1. Introduction x
1.1. Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Related Documentation 1.7. F-Tile Ethernet Multirate IP Core Features and Constraints 1.8. F-Tile Ethernet Multirate IP Core Concepts
1.8. F-Tile Ethernet Multirate IP Core Concepts x
1.8.1. Reconfiguration Group 1.8.2. Base Profile 1.8.3. Secondary Profile 1.8.4. Secondary Profile Group 1.8.5. Startup Profile 1.8.6. Supported Reconfiguration Groups 1.8.7. PTP Timestamp Accuracy Support 1.8.8. Transceiver Lane Mapping
2. Interface Overview x
2.1. Port Numbering Scheme 2.2. Clock Signals 2.3. Reset Signals 2.4. Fractured MAC Segmented Interface for FGT Transceivers 2.5. Fractured MAC Segmented Interface for FHT Transceivers 2.6. Fractured MAC Avalon ST Client Interface for FGT Transceivers 2.7. Fractured MAC Avalon ST Client Interface for FHT Transceivers 2.8. Fractured MII PCS-Only Interface for FGT Transceivers 2.9. Fractured MII PCS-Only Interface for FHT Transceivers 2.10. Fractured PCS66 Interface for OTN/FlexE for FGT Transceivers 2.11. Fractured PCS66 Interface for OTN/FlexE for FHT Transceivers 2.12. MAC Flow Control Interface 2.13. Status Interface 2.14. Avalon® Memory-Mapped Reconfiguration Interfaces 2.15. Auto-Negotiation and Link Training Interface 2.16. Precision Time Protocol Interface
2.16. Precision Time Protocol Interface x
2.16.1. PTP Clock Interface 2.16.2. Time-of-Day Interface 2.16.3. TX 2-Step Timestamp Interface 2.16.4. TX 1-Step Timestamp Interface 2.16.5. RX Timestamp Interface 2.16.6. PTP Status Interface 2.16.7. PTP Tile Interface
4. Designing with the IP Core x
4.1. Specifying the IP Core Parameters and Options 4.2. Generated File Structure
4.1. Specifying the IP Core Parameters and Options x
4.1.1. Reference and System PLL Clock for your IP Design
5. Block Description x
5.1. Precision Time Protocol
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. F-Tile Ethernet Multirate Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide

1.8.8. Transceiver Lane Mapping

The transceiver lane mapping defines a predictable mapping to the EMIBs or demaping from the EMIBs. Transceiver lane mappings specifies transceiver lane assignments for each supported profile within a reconfiguration group.

The below restriction tables specify the maximum number of ports and the maximum number of transceiver lanes defined for each reconfiguration group.

Table 8.  Reconfiguration Group Restrictions using Two Transceiver Lanes
Transceiver Lane /

Number of ports

 FGT / FHT1 FGT / FHT0
1 port using 2 lanes Port 0, Lane 0 Port 0, Lane 1
2 ports using 1 lane each Port 0, Lane 0 Port 1, Lane 0

Table 9.  Reconfiguration Group Restrictions Using Four Transceiver Lanes
Note: All 4x lanes must be part of a single FGT QUAD.
Transceiver Lane /

Number of ports

 FGT / FHT3 FGT / FHT2 FGT / FHT1 FGT / FHT0
1 port using 4 lanes Port 0, Lane 0 Port 0, Lane 1 Port 0, Lane 2 Port 0, Lane 3
1 port using 2 lanes Port 0, Lane 0 Port 0, Lane 1 Unused Unused
1 port using 1 lane Port 0, Lane 0 Unused Unused Unused
2 ports using 2 lanes each Port 0, Lane 0 Port 0, Lane 1 Port 2, Lane 0 Port 2, Lane 1
2 ports using 1 lane each Port 0, Lane 0 Port 2, Lane 0 Unused Unused
4 ports using 1 lane each Port 0, Lane 0 Port 1, Lane 0 Port 2, Lane 0 Port 3, Lane 0
Table 10.  Reconfiguration Group Restrictions Using Eight Transceiver Lanes
Note: All 8x lanes must be assigned to two adjoining QUADs.
Transceiver Lane /

Number of ports

 FGT7 FGT6 FGT5 FGT4 FGT3 FGT2 FGT1 FGT0
1 port using 8 lanes Port 0, Lane 0 Port 0, Lane 1 Port 0, Lane 2 Port 0, Lane 3 Port 0, Lane 4 Port 0, Lane 5 Port 0, Lane 6 Port 0, Lane 7
2 ports using 4x lanes each Port 0, Lane 0 Port 0, Lane 1 Port 0, Lane 2 Port 0, Lane 3 Port 2, Lane 0 Port 2, Lane 1 Port 2, Lane 2 Port 2, Lane 3
4 ports using 2x lanes each Port 0, Lane 0 Port 0, Lane 1 Port 1, Lane 0 Port 1, Lane 1 Port 2, Lane 0 Port 2, Lane 1 Port 3, Lane 0 Port 3, Lane 1
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