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Ixiasoft
2.1. Port Numbering Scheme
2.2. Clock Signals
2.3. Reset Signals
2.4. Fractured MAC Segmented Interface for FGT Transceivers
2.5. Fractured MAC Segmented Interface for FHT Transceivers
2.6. Fractured MAC Avalon ST Client Interface for FGT Transceivers
2.7. Fractured MAC Avalon ST Client Interface for FHT Transceivers
2.8. Fractured MII PCS-Only Interface for FGT Transceivers
2.9. Fractured MII PCS-Only Interface for FHT Transceivers
2.10. Fractured PCS66 Interface for OTN/FlexE for FGT Transceivers
2.11. Fractured PCS66 Interface for OTN/FlexE for FHT Transceivers
2.12. MAC Flow Control Interface
2.13. Status Interface
2.14. Avalon® Memory-Mapped Reconfiguration Interfaces
2.15. Auto-Negotiation and Link Training Interface
2.16. Precision Time Protocol Interface
Visible to Intel only — GUID: hpr1646335687864
Ixiasoft
2.16.7. PTP Tile Interface
A 1-bit ptp_link signal is available per each F-tile Ethernet Multirate IP core. When PTP is enabled, you must connect the PTP link port of one or more Ethernet Multirate IP to the PTP Tile Adapter. The Support Logic Generation step in the Quartus® Prime software automatically generates the actual PTP signals between the F-Tile Ethernet Multirate IP core's PTP soft logic and the PTP tile adapter.
Note: When PTP is enabled, F-tile Ethernet Multirate IP automatically generates the F-tile PTP adapter.
The table displays the interface details for different numbers of ports.
Maximum Number of Ports | Signal Name |
---|---|
1, 2, or 4 | ptp_link |