F-Tile Ethernet Multirate Intel® FPGA IP User Guide

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ID 714307
Date 5/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. F-Tile Ethernet Multirate Intel FPGA IP User Guide Archives 8. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide
1. Introduction x
1.1. Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Related Documentation 1.7. F-Tile Ethernet Multirate IP Core Features and Constraints 1.8. F-Tile Ethernet Multirate IP Core Concepts
1.8. F-Tile Ethernet Multirate IP Core Concepts x
1.8.1. Reconfiguration Group 1.8.2. Base Profile 1.8.3. Secondary Profile 1.8.4. Secondary Profile Group 1.8.5. Startup Profile 1.8.6. Supported Reconfiguration Groups 1.8.7. PTP Timestamp Accuracy Support 1.8.8. Transceiver Lane Mapping
2. Interface Overview x
2.1. Port Numbering Scheme 2.2. Clock Signals 2.3. Reset Signals 2.4. Fractured MAC Segmented Interface for FGT Transceivers 2.5. Fractured MAC Segmented Interface for FHT Transceivers 2.6. Fractured MAC Avalon ST Client Interface for FGT Transceivers 2.7. Fractured MAC Avalon ST Client Interface for FHT Transceivers 2.8. Fractured MII PCS-Only Interface for FGT Transceivers 2.9. Fractured MII PCS-Only Interface for FHT Transceivers 2.10. Fractured PCS66 Interface for OTN/FlexE for FGT Transceivers 2.11. Fractured PCS66 Interface for OTN/FlexE for FHT Transceivers 2.12. MAC Flow Control Interface 2.13. Status Interface 2.14. Avalon® Memory-Mapped Reconfiguration Interfaces 2.15. Auto-Negotiation and Link Training Interface 2.16. Precision Time Protocol Interface
2.16. Precision Time Protocol Interface x
2.16.1. PTP Clock Interface PTP Timestamp Accuracy in Basic Mode PTP Timestamp Accuracy in Advanced Mode 2.16.2. Time-of-Day Interface 2.16.3. TX 2-Step Timestamp Interface 2.16.4. TX 1-Step Timestamp Interface 2.16.5. RX Timestamp Interface 2.16.6. PTP Status Interface 2.16.7. PTP Tile Interface
4. Designing with the IP Core x
4.1. Specifying the IP Core Parameters and Options 4.2. Generated File Structure
4.1. Specifying the IP Core Parameters and Options x
4.1.1. Reference and System PLL Clock for your IP Design
5. Block Description x
5.1. Precision Time Protocol
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. F-Tile Ethernet Multirate Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide

2.16.1. PTP Clock Interface

A separate time-of-day (TOD) clock interface is available for each port within a reconfiguration group. Every clock port in a reconfiguration group must be driven regardless of the number of active ports being used.

The IP core supports two timestamps accuracy modes, Basic and Advanced. In advanced mode, additional logic generates the high accuracy PTP timestamps.

PTP Timestamp Accuracy in Basic Mode

When you select Basic in the Timestamp accuracy mode under PTP tab in the parameter editor for F-Tile Ethernet Multirate IP core, TX and RX data paths of multiple Ethernet IP instances share a single TOD clock output. The time-of-day (TOD) module can be shared across multiple IP instances of different data rates.

Figure 4. TOD Clock Connections for PTP in Basic Accuracy ModeThe figure displays recommended TOD clock connection.

PTP Timestamp Accuracy in Advanced Mode

When you select Advanced in the Timestamp accuracy mode under PTP tab in the parameter editor, the IP core requires a dedicated TOD modules for both, TX and RX data path of each port.

Figure 5. TOD Clock Connections for PTP in Advanced Accuracy ModeThe figure displays recommended TOD clock connection.
In your design, you can share the TX TOD across multiple instances. Follow these conditions when sharing TX TOD:
  • TX transceiver reference clocks of each port are shared, or from the source with the same clock frequency PPM.
  • TX transceiver channel that output the clock driving the shared TOD must not reset after the TX_div clock is stable.
  • While other ports are active, the IP does not allow dynamic reconfiguration to the port output that shared TX_div clock. A dynamic reconfiguration of all ports together is allowed.
  • All ports operate at the same Ethernet rate.
Figure 6. TOD Clock Connections for PTP in Advanced Accuracy Mode: Sharing TX TOD

If you need to dynamically reconfigure your design to support 10GB Ethernet with PTP in Advanced Accuracy Mode, Intel® recommends the following TOD connection.

A single instance of TOD Synchronizer can only support a single synchronization mode, therefore a dedicated TOD module is needed for each rate in TX and RX PTP data path of each port. You must correctly configure the TOD multiplexer according to the current operating state.

Figure 7. TOD Clock Connections for PTP in Advanced Accuracy Mode to support 10G Dynamic Reconfiguration
In your design, you can share TX TOD across multiple instances. Follow these conditions when sharing TX TOD:
  • TX transceiver reference clocks of each port are shared, or from the source with the same clock frequency PPM
  • TX transceiver channel that output the clock driving the shared TOD must not reset after the TX_div clock is stable
  • While other ports are active, the IP does not allow dynamic reconfiguration to the port output that shared TX_div clock. A dynamic reconfiguration of all ports together is allowed.
  • All ports operate at the same Ethernet rate
Figure 8. TOD Clock Connections in Advanced Accuracy Mode to support 10G Dynamic Reconfiguration: Sharing TX TOD
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