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2.1. Port Numbering Scheme
2.2. Clock Signals
2.3. Reset Signals
2.4. Fractured MAC Segmented Interface for FGT Transceivers
2.5. Fractured MAC Segmented Interface for FHT Transceivers
2.6. Fractured MAC Avalon ST Client Interface for FGT Transceivers
2.7. Fractured MAC Avalon ST Client Interface for FHT Transceivers
2.8. Fractured MII PCS-Only Interface for FGT Transceivers
2.9. Fractured MII PCS-Only Interface for FHT Transceivers
2.10. Fractured PCS66 Interface for OTN/FlexE for FGT Transceivers
2.11. Fractured PCS66 Interface for OTN/FlexE for FHT Transceivers
2.12. MAC Flow Control Interface
2.13. Status Interface
2.14. Avalon® Memory-Mapped Reconfiguration Interfaces
2.15. Auto-Negotiation and Link Training Interface
2.16. Precision Time Protocol Interface
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1.4. Device Speed Grade Support
The F-Tile Ethernet Multirate Intel® FPGA IP core supports the following speed grades for Agilex™ 7 and Agilex™ 9 devices:
- Core speed grade: -1 or -2 or -3
Note: Intel recommends -1 or -2 core speed grades for IP core variation with PTP.
In addition to the restrictions listed above, not all dynamic reconfiguration profiles are supported by all device transceiver and core speed grades. For a concise list of Ethernet protocol support by transceiver and core speed grade, refer to Device Speed Grade Support in the F-Tile Ethernet Intel® FPGA Hard IP User Guide.
For information about the applicable device speed grades based on the target data rates, refer to the following tables in Agilex™ 7 Device Data Sheet:
- Table: F-Tile FHT Transmitter and Receiver Data Rate Performance for Agilex™ 7 Devices
- Table: F-Tile FGT Transmitter and Receiver Data Rate Performance for Agilex™ 7 Devices