F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide

Download PDF
ID 710578
Date 12/04/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. F-Tile CPRI PHY Multirate Intel FPGA IP User Guide Archives 8. Document Revision History for the F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide
1. Introduction x
1.1. IP Core Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Related Documentation
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. TX MII Interface (64b/66b) 2.4. RX MII Interface (64b/66b) 2.5. Status Interface for 64b/66b Line Rate 2.6. TX Interface (8b/10b) 2.7. RX Interface (8b/10b) 2.8. Status Interface for 8b/10b Line Rate 2.9. TX Tunnel Interface 2.10. Using TX Tunnel Interface 2.11. RX Tunnel Interface 2.12. Using RX Tunnel Interface 2.13. Status Interface for Tunnel Line Rate 2.14. Serial Interface 2.15. CPRI PHY Reconfiguration Interface 2.16. Datapath Avalon Memory-Mapped Interface 2.17. PMA Avalon Memory-Mapped Interface
2.1. Clock Signals x
2.1.1. Required Clock Frequencies
3. Parameters x
3.1. Sub Profile Parameters Validation
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Dynamic Reconfiguration Settings
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
5. Block Description x
5.1. Latency Measurement 5.2. CDR Clock Output 5.3. RX PMA Adaptation
5.1. Latency Measurement x
5.1.1. Deterministic Latency 5.1.2. Calculation for 64b/66b Datapath
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. F-Tile CPRI PHY Multirate Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide

2.6. TX Interface (8b/10b)

The TX 8b/10b interface is available only if you enable the Enable reconfiguration to 8b/10b datapath parameter or if you select the 8b/10b CPRI line rate. For the CPRI PHY core to power up in the 64b/66b line rate, the IP core asserts these signals when you reconfigure the core at runtime to enter the 8b/10b line rate.

Table 14.  TX 8b/10b Interface
Port Name Width (Bits) Domain Description
i_tx_d[15:0] 16 o_tx_clkout2 Indicates 8b/10b TX data for the corresponding CPRI PHY channel.
i_tx_c[1:0] 2 o_tx_clkout2 Indicates 8b/10b TX control for the corresponding CPRI PHY channel.
When you transmit the data using the TX 8b/10b interface:
  • The frames are 8b/10b encoded. Each byte in i_tx_d has a corresponding bit in i_tx_c that indicates whether the byte is a control byte or a data byte. For example, i_tx_c[1] is the control bit for i_tx_d[15:8].
  • The byte order for the TX interface flows from right to left and the first byte that the core transmits is i_tx_d[7:0].
  • The first bit that the core transmits is i_tx_d[0].
Level Two Title