F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide

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ID 710578
Date 12/04/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. F-Tile CPRI PHY Multirate Intel FPGA IP User Guide Archives 8. Document Revision History for the F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide
1. Introduction x
1.1. IP Core Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Related Documentation
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. TX MII Interface (64b/66b) 2.4. RX MII Interface (64b/66b) 2.5. Status Interface for 64b/66b Line Rate 2.6. TX Interface (8b/10b) 2.7. RX Interface (8b/10b) 2.8. Status Interface for 8b/10b Line Rate 2.9. TX Tunnel Interface 2.10. Using TX Tunnel Interface 2.11. RX Tunnel Interface 2.12. Using RX Tunnel Interface 2.13. Status Interface for Tunnel Line Rate 2.14. Serial Interface 2.15. CPRI PHY Reconfiguration Interface 2.16. Datapath Avalon Memory-Mapped Interface 2.17. PMA Avalon Memory-Mapped Interface
2.1. Clock Signals x
2.1.1. Required Clock Frequencies
3. Parameters x
3.1. Sub Profile Parameters Validation
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Dynamic Reconfiguration Settings
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
5. Block Description x
5.1. Latency Measurement 5.2. CDR Clock Output 5.3. RX PMA Adaptation
5.1. Latency Measurement x
5.1.1. Deterministic Latency 5.1.2. Calculation for 64b/66b Datapath
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. F-Tile CPRI PHY Multirate Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide

4.4. Dynamic Reconfiguration Settings

When you generate the IP, the UX transceiver and EHIP relative location assignment of the sub profiles (profile 1 onwards) are generated at the IP QIP file. The value of these assignments is 0 from the profile 0 (power up).
Figure 11. Sub Profile Relative Location Assignment
When you generate the IP, the necessary IP reconfiguration assignments are generated in IP QIP file. Brief explanation of these assignments:
  • Create a reconfiguration group using the IP_RECONFIG_GROUP_TYPE assignment.
  • Assign all the profiles (power up and sub) to the above reconfiguration group using the IP_RECONFIG_GROUP assignment.
  • Specify the start-up profile using the IP_RECONFIG_GROUP_STARTUP_INSTANCE ON assignment. By default, the start-up profile is the power up profile.
  • Specify the shared sip instance of the IP using the IP_RECONFIG_GROUP_SHARED_SIP ON assignment. This must always be the power up profile.
  • Specify the clocking master instance of the IP using the IP_RECONFIG_GROUP_MASTER_CLOCK_CHANNEL assignment. This must always be the power up profile.
  • Assign all profiles (power up and sub) with a relative reconfig ID using the IP_RECONFIG_ID assignment.

For more information on the dynamic reconfiguration settings, refer to the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide.

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