F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide

Download PDF
ID 710578
Date 12/04/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. F-Tile CPRI PHY Multirate Intel FPGA IP User Guide Archives 8. Document Revision History for the F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide
1. Introduction x
1.1. IP Core Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Related Documentation
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. TX MII Interface (64b/66b) 2.4. RX MII Interface (64b/66b) 2.5. Status Interface for 64b/66b Line Rate 2.6. TX Interface (8b/10b) 2.7. RX Interface (8b/10b) 2.8. Status Interface for 8b/10b Line Rate 2.9. TX Tunnel Interface 2.10. Using TX Tunnel Interface 2.11. RX Tunnel Interface 2.12. Using RX Tunnel Interface 2.13. Status Interface for Tunnel Line Rate 2.14. Serial Interface 2.15. CPRI PHY Reconfiguration Interface 2.16. Datapath Avalon Memory-Mapped Interface 2.17. PMA Avalon Memory-Mapped Interface
2.1. Clock Signals x
2.1.1. Required Clock Frequencies
3. Parameters x
3.1. Sub Profile Parameters Validation
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Dynamic Reconfiguration Settings
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
5. Block Description x
5.1. Latency Measurement 5.2. CDR Clock Output 5.3. RX PMA Adaptation
5.1. Latency Measurement x
5.1.1. Deterministic Latency 5.1.2. Calculation for 64b/66b Datapath
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. F-Tile CPRI PHY Multirate Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide

5.1.2. Calculation for 64b/66b Datapath

If the 64b/66b datapath RSFEC is enabled, perform the following steps to configure the DL logic in F-tile before the RX latency calculation:
  1. Ensure the o_rx_blocklock signal is asserted.
  2. Read the RSFEC code word position value from rsfec_cw_pos_rx register, num field using the Datapath Avalon memory-mapped interface. For more information, refer to the F-Tile Ethernet Intel FPGA Hard IP Register Map.
  3. Program the RSFEC code word position value to FGT fgt_q_dl_ctrl_a_l<x> register, cfg_rx_lat_bit_for_async field using the PMA Avalon memory-mapped interface. The fgt_q_dl_ctrl_a_l<x> register is based on the placement of the FGT transceiver:
    1. FGT15, FGT11, FGT7, FGT3: fgt_q_dl_ctrl_a_l3
    2. FGT14, FGT10, FGT6, FGT2: fgt_q_dl_ctrl_a_l2
    3. FGT13, FGT9, FGT5, FGT1: fgt_q_dl_ctrl_a_l1
    4. FGT12, FGT8, FGT4, FGT0: fgt_q_dl_ctrl_a_l0
    For more information, refer to the F-Tile PMA/FEC Direct PHY Intel FPGA IP Register Map.
  4. Reset the deterministic measure logic for RX datapath by asserting the rx_dl_restart bit at register offset 0x8 using the reconfig_cpri interface.
  5. Release the reset for deterministic measure logic for RX datapath by clearing the rx_dl_restart bit at register offset 0x8 using the reconfig_cpri interface.
Level Two Title