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2.1. Clock Signals
2.2. Reset Signals
2.3. TX MII Interface (64b/66b)
2.4. RX MII Interface (64b/66b)
2.5. Status Interface for 64b/66b Line Rate
2.6. TX Interface (8b/10b)
2.7. RX Interface (8b/10b)
2.8. Status Interface for 8b/10b Line Rate
2.9. TX Tunnel Interface
2.10. Using TX Tunnel Interface
2.11. RX Tunnel Interface
2.12. Using RX Tunnel Interface
2.13. Status Interface for Tunnel Line Rate
2.14. Serial Interface
2.15. CPRI PHY Reconfiguration Interface
2.16. Datapath Avalon Memory-Mapped Interface
2.17. PMA Avalon Memory-Mapped Interface
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4. Designing with the IP Core
The following sections explain how to install, parameterize, simulate, and initialize the F-Tile CPRI PHY Multirate Intel® FPGA IP core.