F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide

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ID 710578
Date 12/04/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. F-Tile CPRI PHY Multirate Intel FPGA IP User Guide Archives 8. Document Revision History for the F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide
1. Introduction x
1.1. IP Core Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Related Documentation
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. TX MII Interface (64b/66b) 2.4. RX MII Interface (64b/66b) 2.5. Status Interface for 64b/66b Line Rate 2.6. TX Interface (8b/10b) 2.7. RX Interface (8b/10b) 2.8. Status Interface for 8b/10b Line Rate 2.9. TX Tunnel Interface 2.10. Using TX Tunnel Interface 2.11. RX Tunnel Interface 2.12. Using RX Tunnel Interface 2.13. Status Interface for Tunnel Line Rate 2.14. Serial Interface 2.15. CPRI PHY Reconfiguration Interface 2.16. Datapath Avalon Memory-Mapped Interface 2.17. PMA Avalon Memory-Mapped Interface
2.1. Clock Signals x
2.1.1. Required Clock Frequencies
3. Parameters x
3.1. Sub Profile Parameters Validation
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Dynamic Reconfiguration Settings
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
5. Block Description x
5.1. Latency Measurement 5.2. CDR Clock Output 5.3. RX PMA Adaptation
5.1. Latency Measurement x
5.1.1. Deterministic Latency 5.1.2. Calculation for 64b/66b Datapath
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. F-Tile CPRI PHY Multirate Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide

1.1. IP Core Overview

The F-Tile CPRI PHY Multirate Intel® FPGA IP core is a multirate version of the F-Tile CPRI PHY Intel® FPGA IP core that supports the dynamic reconfiguration flow in the Intel Agilex® 7 devices with F-tile. This IP core provides various options to specify the power up settings, and targeted dynamic reconfiguration profiles for your design.

During the IP generation, the F-Tile CPRI PHY Multirate Intel® FPGA IP instantiates the F-Tile CPRI PHY Intel® FPGA IP in accordance to the power up settings and dynamic reconfiguration profiles. The F-Tile CPRI PHY Multirate Intel® FPGA IP core supports the following features:
  • Compliant with the Common Public Radio Interface (CPRI) v7.0 Specification (2015-10-09).
  • Supports line bit rates of;
    • 1.2288 Gbps
    • 2.4576 Gbps
    • 3.072 Gbps
    • 4.9152 Gbps
    • 6.144 Gbps
    • 9.8304 Gbps
    • 10.1376 Gbps with and without RS-FEC
    • 12.16512 Gbps with and without RS-FEC
    • 24.33024 Gbps with and without RS-FEC
  • Provides register access interface to external or on-chip processor, using the Intel® Avalon® memory-mapped interconnect specification.
  • Supports Physical Medium Attachment (PMA) adaptation.
Table 1.  Available Features
CPRI Line Bit Rate (Gbps) RS-FEC Support Deterministic Latency Support
1.2288 No Yes
2.4576 No Yes
3.072 No Yes
4.9152 No Yes
6.144 No Yes
9.8304 No Yes
10.1376 With and Without Yes
12.16512 With and Without Yes
24.33024 With and Without Yes
Important: The main purpose of the F-Tile CPRI PHY Multirate Intel® FPGA IP core is dynamic reconfiguration application. For design example, refer to the F-Tile Dynamic Reconfiguration Design Example User Guide.
Related Information
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