F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide

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ID 710578
Date 12/04/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. F-Tile CPRI PHY Multirate Intel FPGA IP User Guide Archives 8. Document Revision History for the F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide
1. Introduction x
1.1. IP Core Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Related Documentation
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. TX MII Interface (64b/66b) 2.4. RX MII Interface (64b/66b) 2.5. Status Interface for 64b/66b Line Rate 2.6. TX Interface (8b/10b) 2.7. RX Interface (8b/10b) 2.8. Status Interface for 8b/10b Line Rate 2.9. TX Tunnel Interface 2.10. Using TX Tunnel Interface 2.11. RX Tunnel Interface 2.12. Using RX Tunnel Interface 2.13. Status Interface for Tunnel Line Rate 2.14. Serial Interface 2.15. CPRI PHY Reconfiguration Interface 2.16. Datapath Avalon Memory-Mapped Interface 2.17. PMA Avalon Memory-Mapped Interface
2.1. Clock Signals x
2.1.1. Required Clock Frequencies
3. Parameters x
3.1. Sub Profile Parameters Validation
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Dynamic Reconfiguration Settings
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
5. Block Description x
5.1. Latency Measurement 5.2. CDR Clock Output 5.3. RX PMA Adaptation
5.1. Latency Measurement x
5.1.1. Deterministic Latency 5.1.2. Calculation for 64b/66b Datapath
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. F-Tile CPRI PHY Multirate Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide

2.1. Clock Signals

Each CPRI PHY channel has its own pair of datapath clocks and each transceiver has its own reference clock. The reconfiguration clock is shared.
Table 6.  CPRI PHY Clock Input Signals
Port name Width (Bits) Description
system_pll_clk_link 1 System PLL clock link port. Connect this port to the F-Tile Reference and System PLL Clocks Intel FPGA IP.
tx_pll_refclk_hs_link 1 TX PLL reference clock link port for high-speed CPRI data rate. Connect this port to the F-Tile Reference and System PLL Clocks Intel FPGA IP.
tx_pll_refclk_ls_ink 1 TX PLL reference clock link port for low-speed CPRI data rate. Connect this port to the F-Tile Reference and System PLL Clocks Intel FPGA IP.
rx_cdr_refclk_hs_link 1 RX CDR reference clock link port for high-speed CPRI data rate. Connect this port to the F-Tile Reference and System PLL Clocks Intel FPGA IP.
rx_cdr_refclk_ls_link 1 RX CDR reference clock link port for low-speed CPRI data rate. Connect this port to the F-Tile Reference and System PLL Clocks Intel FPGA IP.
rx_cdr_divclk_link 1 CDR divided output clock link port. Connect this port to the F-Tile Reference and System PLL Clocks Intel FPGA IP.
i_reconfig_clk 1 Reconfiguration clock.
i_sampling_clk 1 Sampling clock for deterministic latency logic.
Table 7.  Clock Source SignalsThis table lists the clock source ports for the CPRI core. The IP core provides locally generated PLL clocks and recovered clocks that can be used for the datapath.
Signal Name Width (Bits) I/O Direction Description
o_tx_clkout 1 Output System clock divided by 2.
o_tx_clkout2 1 Output Parallel TX clock:
  • For 64B/66B PCS, running at line rate/66.
  • For 8B/10B PCS, running at line rate/20.
  • For tunneling, running at line rate/32.

Hold circuits using this clock in reset until o_tx_pll_lock is high.

o_rx_clkout 1 Output System clock divided by 2.
o_rx_clkout2 1 Output Parallel RX recovered clock:
  • For 64B/66B PCS, running at line rate/66.
  • For 8B/10B PCS, running at line rate/20.

Hold circuits using this clock in reset until o_rx_cdr_lock is high.

Table 8.  Clock Status SignalsThis table lists the clock status ports for the CPRI core. Use these ports to hold the circuits that use clock sources from the IP core in reset until the PLLs driving the clocks are locked.
Signal Name Width (Bits) I/O Direction Description
o_tx_pll_lock 1 Output Indicates the TX PLL driving clock signals from the core is locked.

Do not use the o_tx_clkout or o_tx_clkout2 clocks until the o_tx_pll_lock clock is high.

o_rx_cdr_lock 1 Output Indicates that the recovered clocks are locked to data.

Do not use the o_rx_clkout or o_rx_clkout2 clocks until the o_rx_cdr_lock clock is high.


Section Content
Required Clock Frequencies

Level Two Title