F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide

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ID 710578
Date 12/04/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. F-Tile CPRI PHY Multirate Intel FPGA IP User Guide Archives 8. Document Revision History for the F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide
1. Introduction x
1.1. IP Core Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Related Documentation
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. TX MII Interface (64b/66b) 2.4. RX MII Interface (64b/66b) 2.5. Status Interface for 64b/66b Line Rate 2.6. TX Interface (8b/10b) 2.7. RX Interface (8b/10b) 2.8. Status Interface for 8b/10b Line Rate 2.9. TX Tunnel Interface 2.10. Using TX Tunnel Interface 2.11. RX Tunnel Interface 2.12. Using RX Tunnel Interface 2.13. Status Interface for Tunnel Line Rate 2.14. Serial Interface 2.15. CPRI PHY Reconfiguration Interface 2.16. Datapath Avalon Memory-Mapped Interface 2.17. PMA Avalon Memory-Mapped Interface
2.1. Clock Signals x
2.1.1. Required Clock Frequencies
3. Parameters x
3.1. Sub Profile Parameters Validation
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Dynamic Reconfiguration Settings
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
5. Block Description x
5.1. Latency Measurement 5.2. CDR Clock Output 5.3. RX PMA Adaptation
5.1. Latency Measurement x
5.1.1. Deterministic Latency 5.1.2. Calculation for 64b/66b Datapath
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. F-Tile CPRI PHY Multirate Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide

2.8. Status Interface for 8b/10b Line Rate

This section lists the status ports for the CPRI PHY 8b/10b line rate. Each CPRI PHY channel has its own status port.
Table 16.  CPRI PHY Status Interface Signals for 8b/10b Interface
Port Name Width (Bits) Domain Description
o_rx_patterndetect 1 o_rx_clkout2 The IP core asserts this signal to indicate that K28.5 has been detected in the current word boundary of o_rx_d or o_rx_c and the received data from the RX PMA achieved the word alignment.

This interface should be observed in conjunction with o_rx_disperr and i_rx_errdetect.

o_rx_disperr[1:0] 2 o_rx_clkout2 The IP core asserts this signal to indicate that the IP received 10-bit code or data group in the current word boundary of o_rx_d or o_rx_c has a disparity error.
  • Bit 0: Indicates status for lower data group.
  • Bit 1: Indicates status for higher data group.
o_rx_errdetect[1:0] 2 o_rx_clkout2 The IP core asserts this signal to indicate that it received 10-bit data group in the o_rx_d or o_rx_c has an 8b/10b code violation.
  • Bit 0: Indicates status for lower data group.
  • Bit 1: Indicates status for higher data group.
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