Visible to Intel only — GUID: qik1574304735999
Ixiasoft
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. Parallel Loopback Design Examples
3. HDCP Over DisplayPort Design Example for Intel® Stratix® 10 Devices
4. DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
5. Revision History for the DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide
2.1. Intel® Stratix® 10 DisplayPort SST Parallel Loopback Design Features
2.2. Creating RX-Only or TX-Only Designs
2.3. Design Components
2.4. Clocking Scheme
2.5. Interface Signals and Parameters
2.6. Hardware Setup
2.7. Simulation Testbench
2.8. DisplayPort Transceiver Reconfiguration Flow
2.9. Transceiver Lane Configurations
Visible to Intel only — GUID: qik1574304735999
Ixiasoft
3.4.5. View the Results
At the end of the demonstration, you will be able to view the results on the HDCP-enabled DisplayPort external sink.
To view the results of the demonstration, follow these steps:
- Power up the Intel FPGA board.
- Change the directory to <project directory>/quartus/ directory.
- Type the following command on the Nios II Command Shell to download the Software Object File (.sof) to the FPGA.
nios2-configure-sof <Intel Quartus Prime project name>.sof
- Power up the HDCP-enabled DisplayPort external source and sink (if you have not done so). The DisplayPort external sink displays the output of your DisplayPort external source.