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1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. Parallel Loopback Design Examples
3. HDCP Over DisplayPort Design Example for Intel® Stratix® 10 Devices
4. DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
5. Revision History for the DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide
2.1. Intel® Stratix® 10 DisplayPort SST Parallel Loopback Design Features
2.2. Creating RX-Only or TX-Only Designs
2.3. Design Components
2.4. Clocking Scheme
2.5. Interface Signals and Parameters
2.6. Hardware Setup
2.7. Simulation Testbench
2.8. DisplayPort Transceiver Reconfiguration Flow
2.9. Transceiver Lane Configurations
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3.4.3.1.2. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files
For hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files
- These two files are sharing the same format
- To identify the correct HDCP1 TX DCP key file for hdcp1x_tx_kmem.v, make sure the first 4 bytes of the file are “0x01, 0x00, 0x00, 0x00”.
- To identify the correct HDCP1 RX DCP key file for hdcp1x_rx_kmem.v, make sure the first 4 bytes of the file are “0x02, 0x00, 0x00, 0x00”.
- The keys in the DCP key files are in little-endian format. To use in kmem files, you must convert them into big-endian.
Figure 16. Byte mapping from HDCP1 TX DCP key file into hdcp1x_tx_kmem.v
This figure shows the exact byte mapping from HDCP1 TX DCP key file into hdcp1x_tx_kmem.v. The same mapping applies to hdcp1x_rx_kmem.v.
Note: The byte number displays in below format:
- Key size in bytes * key number + byte number in current row + constant offset + row size in bytes * row number
- 308*n indicates that each key set has 308 bytes.
- 7*y indicates that each row has 7 bytes.
Figure 17. HDCP1 TX DCP key file filling with junk values
Figure 18. Wire Arrays of hdcp1x_tx_kmem.v
Example of hdcp1x_tx_kmem.v and how its wire arrays map to the example of HDCP1 TX DCP key file in Figure 17