Visible to Intel only — GUID: xgw1475806723185
Ixiasoft
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. Parallel Loopback Design Examples
3. HDCP Over DisplayPort Design Example for Intel® Stratix® 10 Devices
4. DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
5. Revision History for the DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide
2.1. Intel® Stratix® 10 DisplayPort SST Parallel Loopback Design Features
2.2. Creating RX-Only or TX-Only Designs
2.3. Design Components
2.4. Clocking Scheme
2.5. Interface Signals and Parameters
2.6. Hardware Setup
2.7. Simulation Testbench
2.8. DisplayPort Transceiver Reconfiguration Flow
2.9. Transceiver Lane Configurations
Visible to Intel only — GUID: xgw1475806723185
Ixiasoft
2.6. Hardware Setup
The DisplayPort Intel® FPGA IP design example is 8Kp30 capable and performs a loop-through for a standard DisplayPort video stream.
- To run the hardware test, connect a DisplayPort-enabled source device to the DisplayPort FMC daughter card sink input.
- The DisplayPort sink decodes the port into a standard video stream and sends it to the clock recovery core.
- The clock recovery core synthesizes the original video pixel clock to be transmitted together with the received video data.
Note: You require the clock recovery feature to produce video without using a frame buffer.
- The clock recovery core then sends the video data to the DisplayPort source and the Transceiver Native PHY TX block.
- Connect the DisplayPort FMC daughter card source port to a monitor to display the image.
LEDs | Function |
---|---|
USER_LED_G[0] | This LED indicates that the source is successfully lane-trained. At this point, the IP core asserts rx0_vid_locked. |
USER_LED_G[2:1] | These LEDs indicate the RX link rate.
|
USER_LED_R[3:0] | These LEDs illuminate design example lane counts.
|