DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683887
Date 1/07/2022
Public

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3.6.1. HDCP Status Signals

There are several signals that are useful to identify the working condition of the HDCP IP cores. These signals are available at the design example top-level and are tied to the onboard LEDs:

Table 35.  Signal Name
Signal Name

Function

rx_hdcp1_enabled

RX HDCP1x IP Decryption Status

0: Inactive

1: Active

rx_hdcp2_enabled

RX HDCP2x IP Decryption Status

0: Inactive

1: Active

tx_hdcp1_enabled

TX HDCP1x IP Encryption Status

0: Inactive

1: Active

tx_hdcp2_enabled

TX HDCP2x IP Encryption Status

0: Inactive

1: Active

Refer to Table 34 for their respective LED placements.

The active state of these signals indicates that the HDCP IP is authenticated and receiving/sending encrypted video stream. For each direction, only HDCP1x or HDCP2x encryption/decryption status signals is active. For example, if either rx_hdcp1_enabled or rx_hdcp2_enabled is active, the HDCP on the RX side is enabled and decrypting the encrypted video stream from the upstream video source.