Visible to Intel only — GUID: nog1574304740722
Ixiasoft
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. Parallel Loopback Design Examples
3. HDCP Over DisplayPort Design Example for Intel® Stratix® 10 Devices
4. DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
5. Revision History for the DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide
2.1. Intel® Stratix® 10 DisplayPort SST Parallel Loopback Design Features
2.2. Creating RX-Only or TX-Only Designs
2.3. Design Components
2.4. Clocking Scheme
2.5. Interface Signals and Parameters
2.6. Hardware Setup
2.7. Simulation Testbench
2.8. DisplayPort Transceiver Reconfiguration Flow
2.9. Transceiver Lane Configurations
Visible to Intel only — GUID: nog1574304740722
Ixiasoft
3.4.5.1. LED Functions
The LEDs on the board indicates the demonstration status.
LED | Functions |
---|---|
user_led_g[0] |
RX PHY ready status.
|
user_led_g[1] |
RX DisplayPort IP video lock status
|
user_led_g[2] |
RX HDCP1x IP decryption status.
|
user_led_g[3] |
RX HDCP2x IP decryption status.
|
user_led_r[1:0] |
TX data rate.
|
user_led_r[2] |
TX HDCP1x IP encryption status.
|
user_led_r[3] |
TX HDCP2x IP encryption status.
|