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1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. Parallel Loopback Design Examples
3. HDCP Over DisplayPort Design Example for Intel® Stratix® 10 Devices
4. DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
5. Revision History for the DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide
2.1. Intel® Stratix® 10 DisplayPort SST Parallel Loopback Design Features
2.2. Creating RX-Only or TX-Only Designs
2.3. Design Components
2.4. Clocking Scheme
2.5. Interface Signals and Parameters
2.6. Hardware Setup
2.7. Simulation Testbench
2.8. DisplayPort Transceiver Reconfiguration Flow
2.9. Transceiver Lane Configurations
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3.6.2. Modifying HDCP Software Parameters
To facilitate the HDCP debugging process, you can modify the parameters in hdcp.c. Table below summarizes the list of configurable parameters and their functions.
Parameter | Function |
SUPPORT_HDCP1X | Enable HDCP 1.3 on TX side |
SUPPORT_HDCP2X | Enable HDCP 2.3 on TX side |
DEBUG_MODE_HDCP | Enable debug messages for TX HDCP |
REPEATER_MODE | Enable repeater mode for HDCP design example |
To modify the parameters, change the values to the desired values in hdcp.c. Before starting the compilation, make the following change in the build_sw_hdcp.sh:
- Locate the following line and comment it out to prevent the modified software file being replaced by the original files from the Intel® Quartus® Prime Software installation path.
- Run “./build_sw_hdcp.sh” to compile the updated software.
- The generated .elf file can be included into the design through two methods:
- Run “nios2-download -g <elf file name>”. Reset the system after the downloading process is completed to ensure proper functionality.
- Run “quartus_cdb –-update_mif” to update the memory initialization files. Run assembler to generate new .sof file which includes the updated software