The DisplayPort Intel® FPGA IP design examples for Stratix® 10 devices feature a simulating testbench and a hardware design that supports compilation and hardware testing.
The DisplayPort Intel® FPGA IP offers the following design examples:
- DisplayPort SST TX-only
- DisplayPort SST RX-only
- DisplayPort SST parallel loopback with a Pixel Clock Recovery (PCR) module
- DisplayPort SST parallel loopback without a PCR module
- High-bandwidth Digital Content Protection (HDCP) over DisplayPort
When you generate a design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.