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1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. Parallel Loopback Design Examples
3. HDCP Over DisplayPort Design Example for Intel® Stratix® 10 Devices
4. DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
5. Revision History for the DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide
2.1. Intel® Stratix® 10 DisplayPort SST Parallel Loopback Design Features
2.2. Creating RX-Only or TX-Only Designs
2.3. Design Components
2.4. Clocking Scheme
2.5. Interface Signals and Parameters
2.6. Hardware Setup
2.7. Simulation Testbench
2.8. DisplayPort Transceiver Reconfiguration Flow
2.9. Transceiver Lane Configurations
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1.2. Hardware and Software Requirements
Intel uses the following hardware and software to test the design example.
Hardware
- Intel® Stratix® 10 GX FPGA L-tile or H-tile Development Kit
- DisplayPort Source (Graphics Processing Unit (GPU))
- DisplayPort Sink (Monitor)
- Bitec DisplayPort FMC daughter card (Revisions 8.0 to 11.0)
- DisplayPort cables
Software
- Intel® Quartus® Prime Pro Edition (for hardware testing)
- ModelSim* - Intel® FPGA Edition, ModelSim* - Intel® FPGA Starter Edition, (Verilog only), Riviera-PRO* , Xcelium* or VCS* (Verilog only)/ VCS* MX simulator